Phase-locked loop clock circuit for generation of audio sampling clock signals from video reference signals

Claim 1

A circuit for generating audio clock signals at an output terminal from reference clock signals at a reference frequency received at an input terminal, said circuit comprising a phase-locked loop circuit generating a PLL output signal at a PLL output frequency at a PLL output terminal, said phase-locked loop circuit having a first programmable divider circuit connected to said input terminal for generating an output signal at said reference frequency divided by a variable integer A; a first fixed divider circuit connected to said PLL output terminal for generating an output signal at said PLL output frequency divided by an integer B, a multiple of 2; a second programmable divider circuit connected to said first fixed divider circuit for generating an output signal at said first fixed divider circuit output signal frequency divided by a programmable amount C; a circuit for supplying a reference voltage; a voltage-controlled oscillator having an output node connected to said PLL output terminal and an input node connected to said reference voltage supply circuit; a phase detector having first and second input nodes, said first input node connected to an output node of said first programmable divider circuit, said second input node connected to an output node of said second programmable divider circuit, said phase detector generating an output signal indicative of a difference between said first and second programmable divider circuit output signals; a charge pump connected to said phase detector and to said reference voltage supply circuit, said charge pump responsive to said phase detector output signal for varying said reference voltage of said reference voltage supply circuit so that the output frequency of said voltage-controlled oscillator varies; a plurality of second fixed divider circuits, each second fixed divider circuit connected to said PLL output terminal for generating an output signal at said PLL output frequency divided by an integer D, each integer D differing from that of another second fixed divider circuit; and a multiplexer having input terminals connected to output terminals of said second fixed divider circuits, said multiplexer selectively connecting an output terminal of one of said second fixed divider circuits to said circuit output terminal responsive to a programmable control signal.