Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
188 words
A memory device comprising: first and second arrays of memory cells, each array having a plurality of columns and a plurality of rows; an address buffer having a plurality of inputs coupled to receive external address information; a predecoder having a plurality of inputs coupled to a respective plurality of outputs of said address buffer; a first latch and a second latch each having an input coupled to an output of said predecoder; first and second column decoders having outputs respectively coupled to said first and second arrays of memory cells for driving said plurality of columns, and inputs respectively coupled to outputs of said first and second latch; and a CAS buffer for generating internal column address strobe (cas) signals consisting of first and second internal cas signals in response to an external CAS signal; wherein the address buffer receives the internal cas signals consisting of first and second internal cas signals, and said first and said second latches respectively receive the first and second internal cas signals to alteratively address each of the memory arrays to eliminate a predetermined precharge time of the external CAS signal.
Claim 2
Dependent Claim
188 words
A memory device comprising: first and second arrays of memory cells, each array having a plurality of columns and a plurality of rows; an address buffer having a plurality of inputs coupled to receive external address information; a predecoder having a plurality of inputs coupled to a respective plurality of outputs of said address buffer; a first latch and a second latch each having an input coupled to an output of said predecoder; first and second column decoders having outputs respectively coupled to said first and second arrays of memory cells for driving said plurality of columns, and inputs respectively coupled to outputs of said first and second latch; and a CAS buffer for generating internal column address strobe (cas) signals consisting of first and second internal cas signals in response to an external CAS signal; wherein the address buffer receives the internal cas signals consisting of first and second internal cas signals, and said first and said second latches respectively receive the first and second internal cas signals to alteratively address each of the memory arrays to eliminate a predetermined precharge time of the external CAS signal.
Claim 3
Dependent Claim
33 words
A memory device as set forth in claim 1, wherein said first and second internal cas signals are generated respectively in response to each rising and falling edge of the external CAS signals.
Claim 4
Dependent Claim
38 words
A memory device as set forth in claim 1, wherein said first latch generates a first internal column address signal in response to the pre-decoded internal column address signal from said pre-decoder and the first internal cas signal.
Claim 5
Dependent Claim
38 words
A memory device as set forth in claim 1, wherein said second latch generates a second internal column address signal in response to the pre-decoded internal column address signal from said pre-decoder and the second internal cas signal.
Claim 6
Dependent Claim
61 words
A memory device as set forth in claim 1, wherein said first latch is adapted to receive the pre-decoded internal column address signal from said pre-decoder when the first cas signal makes a high to low transition in logic, and to generate the first internal column address signal when the first cas signal makes a low to high transition in logic.
Claim 7
Dependent Claim
61 words
A memory device as set forth in claim 1, wherein said second latch is adapted to receive the pre-decoded internal column address signal from said pre-decoder when the second cas signal makes a high to low transition in logic, and to generate the second internal column address signal when the second cas signal makes a low to high transition in logic.