Patent US5700709A successfully refreshed from Google Patents.
US5700709A
Expired / Lapsed
US
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Method for manufacturing a capacitor for a semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-10-25
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Granted: 1997-12-23
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Expires: 2015-10-25
Abstract
Abstract A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.
Inventors
- 👤 Won-mo Park
- 👤 Jong-Jin Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:39
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D1/60; H10D1/68; H10D1/692; H10D1/696; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
167 words
A method for manufacturing at least one capacitor for a semiconductor device including a semiconductor substrate having a multi-layer gate and insulation structure formed thereon, comprising the steps of: forming a first conductive layer on the gate and insulation structure, said first conductive layer including a portion extending through a contact hole provided in the gate and insulation structure to thereby electrically connect said first conductive layer with an active region of a transistor formed in the substrate; forming a first pattern having a step portion by etching said first conductive layer; forming a first material layer on said first pattern; forming a spacer on said step portion of said first pattern by anisotropically etching said first material layer; forming a second pattern by partially etching said first pattern using said spacer as an etching mask; forming a second conductive layer on a first resultant structure produced by the preceding steps; forming a cylindrical storage electrode by anisotropically etching said second conductive layer; and removing said spacer.
Claim 2
Independent Claim
167 words
A method for manufacturing at least one capacitor for a semiconductor device including a semiconductor substrate having a multi-layer gate and insulation structure formed thereon, comprising the steps of: forming a first conductive layer on the gate and insulation structure, said first conductive layer including a portion extending through a contact hole provided in the gate and insulation structure to thereby electrically connect said first conductive layer with an active region of a transistor formed in the substrate; forming a first pattern having a step portion by etching said first conductive layer; forming a first material layer on said first pattern; forming a spacer on said step portion of said first pattern by anisotropically etching said first material layer; forming a second pattern by partially etching said first pattern using said spacer as an etching mask; forming a second conductive layer on a first resultant structure produced by the preceding steps; forming a cylindrical storage electrode by anisotropically etching said second conductive layer; and removing said spacer.
Claim 3
Dependent Claim
38 words
The method as set forth in claim 1, wherein said first material layer is constituted of a first material having an anisotropic etch rate that is different from that of a second material constituting said first conductive layer.
Claim 4
Dependent Claim
22 words
The method as set forth in claim 2, wherein said first material comprises an oxide, and said second material comprises polycrystalline silicon.
Claim 5
Dependent Claim
37 words
The method as set forth in claim 1, further comprising the steps of: forming a dieletric layer on a second resultant structure produced by the preceding steps; and, forming a third conductive layer on said dieletric layer.
Claim 6
Dependent Claim
23 words
The method as set forth in claim 1, wherein the gate and insulation structure includes a sacrificial layer on the upper surface thereof.
Claim 7
Dependent Claim
46 words
The method as set forth in claim 5, wherein said step of forming a second pattern and said step of forming a cylindrical storage electrode are each performed by using said spacer as an etching mask and said sacrificial layer as an etching end-point detection layer.
Claim 8
Dependent Claim
24 words
The method as set forth in claim 6, wherein the gate and insulation structure further includes an etch-blocking layer disposed underneath said sacrificial layer.
Claim 9
Dependent Claim
17 words
The method as set forth in claim 5, further comprising the step of removing said sacrificial layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |