Method and system for the recovery of an encoder clock from an MPEG-2 transport stream

Claim 3

The method of claim 1, wherein the digital data stream is an MPEG-2 transport stream.

Claim 4

The method of claim 1, wherein N is 16.

Claim 5

The method of claim 1, further comprising the steps of: (a) parsing a plurality of PCR values from the digital data stream; (b) comparing the least significant N bits of each of the plurality of PCR values with the value of the N-bit STC when each of the plurality of PCR values are parsed; and (c) generating a control signal proportional to the difference between each of the plurality of PCR values and the STC value, the control signal adjusting the oscillation frequency of the decoder clock to maintain the decoder clock at the same frequency as the encoder clock.

Claim 6

The method of claim 4, further comprising the step of multiplying the control signal by a scale factor.

Claim 7

The method of claim 5, wherein the scale factor is determined by whether a trend of the differences between each of the plurality of PCR values and the STC value indicates that the frequency of the encoder clock and the decoder clock is approximately the same, or the frequency of the encoder clock and the decoder clock is different.

Claim 8

The method of claim 6, wherein the scale factor is small when the trend indicates that the frequency of the encoder clock and the decoder clock is approximately the same.

Claim 9

The method of claim 1, wherein the frequency of the decoder clock is maintained within 3 Hz of the frequency of the encoder clock.

Claim 10

A clock recovery system for recovering an encoder clock from a digital data stream so that a decoder clock oscillates at approximately the same frequency as the encoder clock in an encoder that generates and encodes a plurality of program clock reference (PCR) values in the digital data stream, each of the plurality of PCR values having a 33 bit base and a 9 bit extension, the clock recovery system comprising: (a) a voltage controlled oscillator for producing a decoder clock, the voltage controlled oscillator having an input that allows the frequency of the decoder clock to be adjusted in proportion to a control signal received on the input; (b) means for parsing a plurality of PCR values from the digital data stream; (c) a divider coupled to the voltage controlled oscillator for dividing the decoder clock to produce a counter clock that is synchronized with the decoder clock; (d) an N-bit counter coupled to the means for parsing a plurality of PCR values from the digital data stream, the N-bit counter having an input that is connected to the divider to produce an N-bit system time clock (STC) that is clocked by the counter clock; (e) means for loading the N-bit counter with a number N of the least significant bits of the 33 bit base of a first one of the plurality of PCR values, N being less than or equal to 33; and (f) an N-bit comparator for comparing a number N of the least significant bits of a second one of a plurality of PCR values with the value of the N-bit STC when the second one of the plurality of PCR values is parsed from the digital data stream, the N-bit comparator generating a control signal indicative of a difference between the second PCR value and the STC value and applying the control signal to the input of the voltage controlled oscillator to adjust the frequency of the decoder clock and maintain the decoder clock produced by the voltage controlled oscillator at approximately the same frequency as the encoder clock.

Claim 11

A clock recovery system for recovering an encoder clock from a digital data stream so that a decoder clock oscillates at approximately the same frequency as the encoder clock in an encoder that generates and encodes a plurality of program clock reference (PCR) values in the digital data stream, each of the plurality of PCR values having a 33 bit base and a 9 bit extension, the clock recovery system comprising: (a) a voltage controlled oscillator for producing a decoder clock, the voltage controlled oscillator having an input that allows the frequency of the decoder clock to be adjusted in proportion to a control signal received on the input; (b) means for parsing a plurality of PCR values from the digital data stream; (c) a divider coupled to the voltage controlled oscillator for dividing the decoder clock to produce a counter clock that is synchronized with the decoder clock; (d) an N-bit counter coupled to the means for parsing a plurality of PCR values from the digital data stream, the N-bit counter having an input that is connected to the divider to produce an N-bit system time clock (STC) that is clocked by the counter clock; (e) means for loading the N-bit counter with a number N of the least significant bits of the 33 bit base of a first one of the plurality of PCR values, N being less than or equal to 33; and (f) an N-bit comparator for comparing a number N of the least significant bits of a second one of a plurality of PCR values with the value of the N-bit STC when the second one of the plurality of PCR values is parsed from the digital data stream, the N-bit comparator generating a control signal indicative of a difference between the second PCR value and the STC value and applying the control signal to the input of the voltage controlled oscillator to adjust the frequency of the decoder clock and maintain the decoder clock produced by the voltage controlled oscillator at approximately the same frequency as the encoder clock.

Claim 12

The clock recovery system of claim 9, wherein N is 16.

Claim 13

The clock recovery system of claim 10, wherein the N-bit counter is comprised of an 8-bit hardware register and an 8-bit software register.

Claim 14

The clock recovery system of claim 10, wherein the N-bit counter is comprised of a 16-bit hardware register.

Claim 15

The clock recovery system of claim 9, wherein the nominal frequency of the decoder clock is 27 MHz.

Claim 16

The clock recovery system of claim 13, wherein the divider divides the decoder clock by 300.

Claim 17

The clock recovery system of claim 9, wherein the control signal is filtered before application to the voltage controlled oscillator.

Claim 18

The clock recovery system of claim 9, wherein the digital data stream is an MPEG-2 transport stream.

Claim 19

The clock recovery system of claim 9, further comprising a controller coupled between the N-bit comparator and the voltage controlled oscillator, the controller monitoring the control signal produced by the N-bit comparator and multiplying the control signal by a scale factor.

Claim 20

The clock recovery system of claim 17, wherein the scale factor is determined by monitoring a trend of the differences between each of the plurality of PCR values and the STC value to determine whether the frequency of the encoder clock and the decoder clock is approximately the same, or the frequency of the encoder clock and the decoder clock is different.

Claim 21

The clock recovery system of claim 18, wherein the scale factor is small when the trend indicates that the frequency of the encoder clock and the decoder clock is approximately the same.

Claim 22

The clock recovery system of claim 9, wherein the frequency of the decoder clock is maintained within 3 Hz of the frequency of the encoder clock.