Zero IF receivers

Claim 2

A zero IF receiver comprising first and second quadrature related frequency down conversion stages, outputs of the first and second frequency down conversion stages being coupled to respective first and second symmetrical gyrator IF filtering stages, means coupled to outputs of the first and second symmetrical gyrator IF filtering stages for deriving an estimate of instantaneous signal amplitude of a received signal, an output of said means being coupled to gain control inputs of said first and second symmetrical gyrator IF filtering stages, wherein each of the first and second symmetrical gyrator IF filtering stages comprises at least one pair of transconductors, and the gain of each said symmetrical gyrator IF filtering stage is controlled by adjusting the ratio of the transconductances of each pair of transconductances thereof in a manner so as to maintain the product of the transconductances of each said pair substantially constant.

Claim 3

A receiver as claimed in claim 1, characterized in that said means for deriving an estimate of the instantaneous signal amplitude comprises means for determining the sum of the squares of the signal amplitudes at the outputs of the first and second gyrator IF filtering stages.

Claim 4

A receiver as claimed in claim 1, characterized in that the number of pairs of transconductors whose ratio of transconductances is adjusted is one less than the order of the filtering stages.

Claim 5

A receiver as claimed in claim 1, characterized in that said means for deriving an estimate of the instantaneous signal amplitude comprises means for determining the sum of the squares of the signal amplitudes at the outputs of the first and second gyrator IF filtering stages and in that the number of pairs of transconductors whose ratio of transconductances is adjusted is one less than the order of the filtering stages.

Claim 6

A zero IF receiver comprising first and second quadrature related frequency down conversion stages, each said stage having an output, first and second symmetrical gyrator IF filtering stages coupled to respective outputs of the first and second frequency down conversion stages, means coupled to the first and second symmetrical gyrator IF filtering stages for deriving an estimate of the instantaneous signal amplitude of the received signal, each of the first and second symmetrical gyrator IF filtering stages comprising at least one pair of transconductors, each of the transconductors of said at least one pair comprising first and second cross connected long tailed pair transconductor circuits and third and fourth cross connected long tailed pair transconductor circuits, the transconductances of the first, second, third and fourth transconductor circuits being adjusted in response to signals from said estimate deriving means to control the gains of the first and second symmetrical gyrator IF filtering stages, said gains being altered by adjusting the ratio of the transconductances of the first and second cross connected long tailed pair transconductor circuits and adjusting the ratio of the transconductances of the third and fourth cross connected long tailed pair transconductor circuits in such a manner as to maintain the product of the transconductances of said first and second transconductor circuits substantially constant and the product of the transconductances of said third and fourth transconductor circuits substantially constant.

Claim 7

A zero IF receiver comprising first and second quadrature related frequency down conversion stages, each said stage having an output, first and second symmetrical gyrator IF filtering stages coupled to respective outputs of the first and second frequency down conversion stages, means coupled to the first and second symmetrical gyrator IF filtering stages for deriving an estimate of the instantaneous signal amplitude of the received signal, each of the first and second symmetrical gyrator IF filtering stages comprising at least one pair of transconductors, each of the transconductors of said at least one pair comprising first and second cross connected long tailed pair transconductor circuits and third and fourth cross connected long tailed pair transconductor circuits, the transconductances of the first, second, third and fourth transconductor circuits being adjusted in response to signals from said estimate deriving means to control the gains of the first and second symmetrical gyrator IF filtering stages, said gains being altered by adjusting the ratio of the transconductances of the first and second cross connected long tailed pair transconductor circuits and adjusting the ratio of the transconductances of the third and fourth cross connected long tailed pair transconductor circuits in such a manner as to maintain the product of the transconductances of said first and second transconductor circuits substantially constant and the product of the transconductances of said third and fourth transconductor circuits substantially constant.

Claim 8

A receiver as claimed in claim 5, characterized in that said means for deriving an estimate of the instantaneous signal amplitude comprises means for determining the sum of the squares of the signal amplitudes at the outputs of the first and second gyrator IF filtering stages.

Claim 9

A receiver as claimed in claim 5, characterized in that the number of pairs of transconductors whose ratio of transconductances is adjusted is one less than the order of the filtering stages.

Claim 10

A receiver as claimed in claim 5, characterized in that said means for deriving an estimate of the instantaneous signal amplitude comprises means for determining the sum of the squares of the signal amplitudes at the outputs of the first and second gyrator IF filtering stages and in that the number of pairs of transconductors whose ratio of transconductances is adjusted is one less than the order of the filtering stages.