US5696912A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-media computer architecture
Assignee: ATI Technologies ULC
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Filing: 1996-07-19
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Granted: 1997-12-09
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Expires: 2016-07-19
Abstract
Abstract A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.
Inventors
- 👤 Robert P. Bicevskis
- 👤 Adrian H. Hartog
- 👤 Gordon Caruk
- 👤 Michael A. Alford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:27
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/366; G09; G09G; G09G2340/00; G09G2340/02; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
190 words
A computer system comprising: (a) at least one of a main bus and an expansion bus operating at a first data rate substantially insufficient to carry video signals, (b) a CPU connected to the main bus, (c) peripherals connected to said one of the main bus or to said expansion buses, (d) a subsystem connected to either of said buses for receiving control, address and data signals from the CPU at said first data rate comprising, (i) a graphics controller, (ii) a data compression circuit, (iii) a video controller, (iv) a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, (v) a memory connected to data input ports of said circuits and controllers via said subsystem bus, (vi) a first arbiter for determining which controller is permitted to access the memory, (vii) a link bus connecting each of said controllers, and (viii) means for providing polling signals to each of said controllers and circuits on the link bus and for receiving acknowledgment signals therefrom, and thereby synchronizing and allowing exchange of control information between the controller sand circuits without enquirying interrupts or intervention from said CPU.
Claim 2
Dependent Claim
190 words
A computer system comprising: (a) at least one of a main bus and an expansion bus operating at a first data rate substantially insufficient to carry video signals, (b) a CPU connected to the main bus, (c) peripherals connected to said one of the main bus or to said expansion buses, (d) a subsystem connected to either of said buses for receiving control, address and data signals from the CPU at said first data rate comprising, (i) a graphics controller, (ii) a data compression circuit, (iii) a video controller, (iv) a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, (v) a memory connected to data input ports of said circuits and controllers via said subsystem bus, (vi) a first arbiter for determining which controller is permitted to access the memory, (vii) a link bus connecting each of said controllers, and (viii) means for providing polling signals to each of said controllers and circuits on the link bus and for receiving acknowledgment signals therefrom, and thereby synchronizing and allowing exchange of control information between the controller sand circuits without enquirying interrupts or intervention from said CPU.
Claim 3
Dependent Claim
22 words
A system as defined in claim 1 in which said means for providing polling signals is comprised of a link bus arbiter.
Claim 4
Dependent Claim
32 words
A system as defined in claim 1 in which the memory has an output for providing signals for display on a computer monitor through a conduction path other than said subsystem bus.
Claim 5
Dependent Claim
27 words
A system as defined in claim 1, in which the designation of which of said circuits may access the memory is determined according to a priority rating.
Claim 6
Dependent Claim
27 words
A system as defined in claim 4 in which the priority rating is determined by a code contained in connections from the devices to the arbiter circuit.
Claim 7
Dependent Claim
45 words
A system as defined in claim 1 in which upon polling and acknowledgment, one of said circuits can broadcast a signal on the link bus designating a particular service request and another service request performing circuit is thereby caused to perform the particular service requested.
Claim 8
Dependent Claim
22 words
A system as defined in claim 6 in which any one designated service is performed by a corresponding one of said circuits.
Claim 9
Dependent Claim
14 words
A system as defined in claim 2, in which said arbiters are the same.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |