First read cycle circuit for semiconductor memory

Claim 2

In a latched memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a first read cycle circuit for initiating a read cycle within said memory array circuit upon the initial application of power by generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit, said first read cycle circuit comprising: a comparator having first and second inputs and an output, said reference voltage coupled to said first input, said word line signal coupled to said second input, said comparator being enabled when said reference voltage valid signal goes active, said output of said comparator being tripped when said word line signal exceeds said reference voltage; clocking means having an input and an output, said output of said comparator coupled to said input of said clocking means, said output of said clocking means coupled to said clock chain circuitry; wherein said reference voltage is chosen such that the tripping of said comparator occurs before said word line signal reaches its full value, said word line signal input to said sense amplifier delay circuit, said sense amplifier delay circuit delaying the availability of output data from said memory array circuit in accordance with the level of said word line signal; and wherein the tripping of said comparator is not dependent on the ramping up of said supply voltage and causes said clocking means to trigger said clock chain circuitry to initiate said read cycle of said memory array circuit thus providing valid data.

Claim 3

The first read cycle circuit according to claim 1, further comprising enable circuitry coupled to said output of said comparator, said enable circuitry disabling said output of said comparator while said reference voltage valid signal indicates that said reference voltage is invalid.

Claim 4

The first read cycle circuit according to claim 1, wherein said comparator comprises an enable circuit, whereby the tripping of said comparator causes the disablement of said comparator after a predetermined time delay, thus reducing power consumption of said circuit.

Claim 5

The first read cycle circuit according to claim 1, wherein said clocking means comprises address transition detection circuitry.

Claim 6

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a first read cycle circuit for initiating a read cycle within said memory array circuit upon the initial application of power by generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit, said first read cycle circuit comprising: a voltage divider having an input and an output, said word line signal coupled to said input; a comparator having first and second inputs and an output, said reference voltage coupled to said first input, said output of said voltage divider coupled to said second input, said comparator being enabled when said reference voltage valid signal goes active, said output of said comparator being tripped when said output of said voltage divider exceeds said reference voltage; clock means having an input and an output, said output of said comparator coupled to said input of said clock means, said output of said clock means coupled to said clock chain circuitry; wherein said voltage divider is suitable tuned such that the tripping of said comparator occurs before said word line signal reaches its full value, said word line signal input to said sense amplifier delay circuit, said sense amplifier delay circuit delaying the availability of output data from said memory array circuit in accordance with the level of said word line signal; and wherein the tripping of said comparator is not dependent on the ramping up of said supply voltage and causes said clock means to trigger said clock chain circuitry to initiate said read cycle of said memory array circuit thus providing valid data.

Claim 7

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a first read cycle circuit for initiating a read cycle within said memory array circuit upon the initial application of power by generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit, said first read cycle circuit comprising: a voltage divider having an input and an output, said word line signal coupled to said input; a comparator having first and second inputs and an output, said reference voltage coupled to said first input, said output of said voltage divider coupled to said second input, said comparator being enabled when said reference voltage valid signal goes active, said output of said comparator being tripped when said output of said voltage divider exceeds said reference voltage; clock means having an input and an output, said output of said comparator coupled to said input of said clock means, said output of said clock means coupled to said clock chain circuitry; wherein said voltage divider is suitable tuned such that the tripping of said comparator occurs before said word line signal reaches its full value, said word line signal input to said sense amplifier delay circuit, said sense amplifier delay circuit delaying the availability of output data from said memory array circuit in accordance with the level of said word line signal; and wherein the tripping of said comparator is not dependent on the ramping up of said supply voltage and causes said clock means to trigger said clock chain circuitry to initiate said read cycle of said memory array circuit thus providing valid data.

Claim 8

The memory array circuit according to claim 5, wherein said reference voltage is a bandgap voltage stable against variations in said supply voltage and temperature.

Claim 9

The first read cycle circuit according to claim 5, further comprising enable circuitry coupled to said output of said comparator, said enable circuitry disabling said output of said comparator while said reference voltage valid signal indicates that said reference voltage is invalid.

Claim 10

The first read cycle circuit according to claim 5, wherein said comparator comprises an enable circuit, whereby the tripping of said comparator causes the disablement of said comparator after a predetermined time delay, thus reducing power consumption of said first read cycle circuit.

Claim 11

The first read cycle circuit according to claim 5, wherein said voltage divider comprises an enable circuit, whereby the tripping of said comparator causes the disablement of said voltage divider after a predetermined time delay, thus reducing power consumption of said first read cycle circuit.

Claim 12

The first read cycle circuit according to claim 5, wherein said clock means comprises address transition detection circuitry.

Claim 13

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a first read cycle circuit for initiating a read cycle within said memory array circuit upon the initial application of power by generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit, said first read cycle circuit comprising: a multiplier having an input and an output, said input of said multiplier coupled to said reference voltage; a comparator having first and second inputs and an output, said word line signal coupled to said first input of said comparator, said output of said multiplier coupled to said second input of said comparator, said comparator being enabled when said reference voltage valid signal goes active, said output of said comparator being tripped when said word line signal exceeds said output of said multiplier; clock means having an input and an output, said output of said comparator coupled to said input of said clock means, said output of said clock means coupled to said clock chain circuitry; wherein said multiplier is suitable tuned such that the tripping of said comparator occurs before said word line signal reaches its full value, said word line signal input to said sense amplifier delay circuit, said sense amplifier delay circuit delaying the availability of output data from said memory array circuit in accordance with the level of said word line signal; and wherein the tripping of said comparator is not dependent on the ramping up of said supply voltage and causes said clock means to trigger said clock chain circuitry to initiate said read cycle of said memory array circuit thus providing valid data.

Claim 14

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a first read cycle circuit for initiating a read cycle within said memory array circuit upon the initial application of power by generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit, said first read cycle circuit comprising: a multiplier having an input and an output, said input of said multiplier coupled to said reference voltage; a comparator having first and second inputs and an output, said word line signal coupled to said first input of said comparator, said output of said multiplier coupled to said second input of said comparator, said comparator being enabled when said reference voltage valid signal goes active, said output of said comparator being tripped when said word line signal exceeds said output of said multiplier; clock means having an input and an output, said output of said comparator coupled to said input of said clock means, said output of said clock means coupled to said clock chain circuitry; wherein said multiplier is suitable tuned such that the tripping of said comparator occurs before said word line signal reaches its full value, said word line signal input to said sense amplifier delay circuit, said sense amplifier delay circuit delaying the availability of output data from said memory array circuit in accordance with the level of said word line signal; and wherein the tripping of said comparator is not dependent on the ramping up of said supply voltage and causes said clock means to trigger said clock chain circuitry to initiate said read cycle of said memory array circuit thus providing valid data.

Claim 15

The memory array circuit according to claim 11, wherein said reference voltage is a bandgap voltage stable against variations in said supply voltage and temperature.

Claim 16

The first read cycle circuit according to claim 11, further comprising enable circuitry coupled to said output of said comparator, said enable circuitry disabling said output of said comparator while said reference voltage valid signal indicates that said reference voltage is invalid.

Claim 17

The first read cycle circuit according to claim 11, wherein said comparator comprises an enable circuit, whereby the tripping of said comparator causes the disablement of said comparator after a predetermined time delay, thus reducing power consumption of said first read cycle circuit.

Claim 18

The first read cycle circuit according to claim 11, wherein said multiplier comprises an enable circuit, whereby the tripping of said comparator causes the disablement of said multiplier after a predetermined time delay, thus reducing power consumption of said first read cycle circuit.

Claim 19

The first read cycle circuit according to claim 11, wherein said clock means comprises address transition detection circuitry.

Claim 20

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: comparing said reference voltage to said word line signal once said reference voltage valid signal goes active; upon said word line signal exceeding said reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 21

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: comparing said reference voltage to said word line signal once said reference voltage valid signal goes active; upon said word line signal exceeding said reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 22

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: dividing said word line signal; comparing said reference voltage to said divided word line signal once said reference voltage valid signal goes active; upon said divided word line signal exceeding said reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 23

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: dividing said word line signal; comparing said reference voltage to said divided word line signal once said reference voltage valid signal goes active; upon said divided word line signal exceeding said reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 24

The method according to claim 18, wherein said reference voltage is a bandgap voltage stable against variations in said supply voltage and temperature.

Claim 25

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: multiplying said reference voltage; comparing said multiplied reference voltage to said word line signal once said reference voltage valid signal goes active; upon said word line signal exceeding said multiplied reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 26

In a memory array circuit utilizing a sense amplifier delay circuit, a supply voltage, a reference voltage, a reference voltage valid signal, a word line signal and clock chain circuitry, a method of initiating a read cycle within said memory array circuit upon the initial application of power, said method comprising the steps of: multiplying said reference voltage; comparing said multiplied reference voltage to said word line signal once said reference voltage valid signal goes active; upon said word line signal exceeding said multiplied reference voltage, generating an output signal active to trigger said clock chain circuitry to initiate said read cycle within said memory array circuit; wherein said step of generating is not dependent on the ramping up of said supply voltage; and wherein said sense amplifier delay circuit delays the availability of output data from said memory array circuit in accordance with the level of said word line signal.

Claim 27

The method according to claim 20, wherein said reference voltage is a bandgap voltage stable against variations in said supply voltage and temperature.