US5696698A
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US
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Device for addressing a cache memory of a compressing motion picture circuit
Assignee: STMicroelectronics SA
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Filing: 1995-04-18
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Granted: 1997-12-09
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Expires: 2015-04-18
Abstract
Abstract A device for addressing a cache memory of a motion picture compression circuit, executing series of comparisons to estimate the motion of a current window of pixels of a current picture with respect to a reference window of a preceding picture, includes a first cache memory partitioned into four physical segments of equal size. Each physical segment is adapted to contain one half-macroblock of the reference window, and a circuit for addressing the first cache memory, the addressing being different for a motion estimation related to a current window of even rank and for a motion estimation related to a current window of odd rank.
Inventors
- 👤 Jean-Claude Herluison
- 👤 Jean-Luc Bauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:09
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/144; H04N5/145; G; G06; G06T; G06T7/00; G06T7/20; G06T7/223; H04N19/00; H04N19/42; H04N19/43; H04N19/433; H04N19/50; H04N19/503; H04N19/51; G06T2207/00; G06T2207/10; G06T2207/10016
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
190 words
In a motion picture compression circuit that executes a series of comparisons to estimate motion of each current window of pixels in a sequence of current windows of a current picture with respect to a corresponding reference window in a sequence of reference windows .of a preceding picture, each current window having a rank that designates its sequential position in the sequence of current windows, the sequence of current windows including a currently processed current window., the sequence of reference windows including a currently processed reference window, a device comprising: a first cache memory partitioned into four physical segments of equal size, each physical segment being adapted to contain one half-macroblock of the currently processed reference window; and means for addressing the first cache memory, when executing the series of comparisons that estimate motion of the currently processed current window with respect to the currently processed reference window, in a first manner when the currently processed current window has an even rank, and in a second manner when the currently processed current window has an odd rank, the first and second manners of addressing the first cache memory being different.
Claim 2
Dependent Claim
190 words
In a motion picture compression circuit that executes a series of comparisons to estimate motion of each current window of pixels in a sequence of current windows of a current picture with respect to a corresponding reference window in a sequence of reference windows .of a preceding picture, each current window having a rank that designates its sequential position in the sequence of current windows, the sequence of current windows including a currently processed current window., the sequence of reference windows including a currently processed reference window, a device comprising: a first cache memory partitioned into four physical segments of equal size, each physical segment being adapted to contain one half-macroblock of the currently processed reference window; and means for addressing the first cache memory, when executing the series of comparisons that estimate motion of the currently processed current window with respect to the currently processed reference window, in a first manner when the currently processed current window has an even rank, and in a second manner when the currently processed current window has an odd rank, the first and second manners of addressing the first cache memory being different.
Claim 3
Dependent Claim
66 words
The device of claim 1, further including: a second cache memory adapted to contain a macroblock of pixels of the currently processed current window; and means for loading the second cache memory with the macroblock of pixels of the currently processed current window before executing the series of comparisons to estimate motion of the currently processed current window with respect to the currently processed reference window.
Claim 4
Dependent Claim
124 words
The device of claim 2, wherein the physical segments of the first cache memory include a first pair of segments and a second pair of segments, and wherein each reference window includes a first pair of half-macroblocks and a second pair of half-macroblocks, the device further including: means for loading, prior to executing the series of comparisons to estimate motion of a next current window in the sequence of current windows with respect to a next reference window, the second pair of half-macroblocks of the next reference window into the first pair of segments of the first cache memory when the next current window has an even rank, and into the second pair of segments when the next current window has an odd rank.
Claim 5
Dependent Claim
115 words
The device of claim 3, wherein each segment stores a half-macroblock, and wherein the device further includes: means for reading the currently processed reference window from the first cache memory by respectively assigning contents of the first and second pairs of segments of the first cache memory to the first and second pairs of half-macroblocks of the currently processed reference window when the currently processed current window has an even rank, and by respectively assigning the contents of the first and second pairs of segments of the first cache memory to the second pair and first pair of half-macroblocks of the currently processed reference window when the currently processed current window has an odd rank.
Claim 6
Independent Claim
279 words
A method for addressing a memory of a motion picture compression circuit that determines a motion estimation of each current macroblock of pixels in a sequence of current macroblocks of a current picture with respect to a corresponding reference window in a sequence of reference windows of a preceding picture, each current macroblock having a rank that designates its sequential position in the sequence of current macroblocks, the method comprising the steps of, for each one of the current macroblocks: A. partitioning one of the reference windows of the preceding picture that corresponds to the one of the current macroblocks into a first half-macroblock, a second half-macroblock, a third half-macroblock, and a fourth half-macroblock, the one of the reference windows including a corresponding macroblock having a position in the preceding picture that corresponds to a position of the one of the current macroblocks in the current picture, the one of the reference windows further including first and second half-macroblocks that are positioned on opposing sides of the corresponding macroblock in the preceding picture; B. partitioning a first cache memory into a first physical segment, a second physical segment, a third physical segment, and a fourth physical segment, each physical segment being adapted to contain one of the half-macroblocks of the one of the reference windows; C. storing in the first cache memory the one of the reference windows; and D. addressing the first cache memory in a first manner when the one of the current macroblocks has an even rank, and in a second manner when the one of the current macroblocks has an odd rank, the first and second manners of addressing the first cache memory being different.
Claim 7
Independent Claim
279 words
A method for addressing a memory of a motion picture compression circuit that determines a motion estimation of each current macroblock of pixels in a sequence of current macroblocks of a current picture with respect to a corresponding reference window in a sequence of reference windows of a preceding picture, each current macroblock having a rank that designates its sequential position in the sequence of current macroblocks, the method comprising the steps of, for each one of the current macroblocks: A. partitioning one of the reference windows of the preceding picture that corresponds to the one of the current macroblocks into a first half-macroblock, a second half-macroblock, a third half-macroblock, and a fourth half-macroblock, the one of the reference windows including a corresponding macroblock having a position in the preceding picture that corresponds to a position of the one of the current macroblocks in the current picture, the one of the reference windows further including first and second half-macroblocks that are positioned on opposing sides of the corresponding macroblock in the preceding picture; B. partitioning a first cache memory into a first physical segment, a second physical segment, a third physical segment, and a fourth physical segment, each physical segment being adapted to contain one of the half-macroblocks of the one of the reference windows; C. storing in the first cache memory the one of the reference windows; and D. addressing the first cache memory in a first manner when the one of the current macroblocks has an even rank, and in a second manner when the one of the current macroblocks has an odd rank, the first and second manners of addressing the first cache memory being different.
Claim 8
Dependent Claim
180 words
The method of claim 5, wherein step D includes, for each one of the current macroblocks: when the one of the current macroblocks has an even rank, addressing the first and second physical segments of the first cache memory as containing the first and second half-macroblocks of the one of the reference windows that corresponds to the one of the current macroblocks and addressing the third and fourth physical segments of the first cache memory as containing the third and fourth half-macroblocks of the one of the reference windows that corresponds to the one of the current macroblocks, and when the one of the current macroblocks has an odd rank, addressing the third and fourth physical segments of the first cache memory as containing the first and second half-macroblocks of the one of the reference windows that corresponds to the one of the current macroblocks, and the first and second physical segments of the first cache memory as containing the third and fourth half-macroblocks of the one of the reference windows that corresponds to the one of the current macroblocks.
Claim 9
Dependent Claim
96 words
The method of claim 6, further including the step of sequentially loading, in a second cache memory, each current macroblock of pixels of the current picture; and wherein step C includes, for each one of the reference windows subsequent to a first reference window in the sequence of reference windows, loading in the first cache memory the third and fourth half-macroblocks of the one of the reference windows, the first and second half-macroblocks of the one of the reference windows having been loaded previously into the first cache memory as part of a preceding reference window.
Claim 10
Dependent Claim
25 words
The method of claim 6, wherein step D is performed using a state machine that controls calculation of each address of the first cache memory.
Claim 11
Independent Claim
166 words
A method for addressing a cache memory during a process that executes a series of operations, each of the operations being executed on a first set of current values and a second set of reference values stored in the cache memory, each of the operations having a rank that defines its sequential position in the series of operations, each set of reference values including at least one value that is used during the execution of two successive operations, the method including the step of: A. partitioning the first set of reference values stored in the cache memory into a first sub-set, a second sub-set, a third sub-set, and a fourth sub-set; B. partitioning the cache memory into a first physical segment, a second physical segment, a third physical segment, and a fourth physical segment, each physical segment being adapted to contain one of the sub-sets of the first set of reference values; and C. addressing the cache memory differently for operations having even and odd ranks.
Claim 12
Independent Claim
166 words
A method for addressing a cache memory during a process that executes a series of operations, each of the operations being executed on a first set of current values and a second set of reference values stored in the cache memory, each of the operations having a rank that defines its sequential position in the series of operations, each set of reference values including at least one value that is used during the execution of two successive operations, the method including the step of: A. partitioning the first set of reference values stored in the cache memory into a first sub-set, a second sub-set, a third sub-set, and a fourth sub-set; B. partitioning the cache memory into a first physical segment, a second physical segment, a third physical segment, and a fourth physical segment, each physical segment being adapted to contain one of the sub-sets of the first set of reference values; and C. addressing the cache memory differently for operations having even and odd ranks.
Claim 13
Dependent Claim
98 words
The method of claim 9, wherein step C includes: addressing the first and second physical segments of the cache memory as containing the first and second sub-sets of the sets of reference values and the third and fourth physical segments as containing the third and fourth sub-sets, for operations having an even rank; and addressing the third and fourth physical segments of the cache memory as containing the first and second sub-sets of the set of reference values and the first and second physical segments as containing the third and fourth sub-sets for operations having an odd rank.
Claim 14
Independent Claim
171 words
A method for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory that stores a first reference picture portion of the series of reference picture portions, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, a second reference picture portion of the series of reference picture portions including the second set of macroblocks and a third set of macroblocks, the method comprising the steps of: A. loading, while maintaining the second set of macroblocks in the cache memory, the third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks that form the second reference picture portion; and B. comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 15
Independent Claim
171 words
A method for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory that stores a first reference picture portion of the series of reference picture portions, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, a second reference picture portion of the series of reference picture portions including the second set of macroblocks and a third set of macroblocks, the method comprising the steps of: A. loading, while maintaining the second set of macroblocks in the cache memory, the third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks that form the second reference picture portion; and B. comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 16
Dependent Claim
41 words
The method of claim 11, wherein the first and third sets of macroblocks are equal in size, and wherein step A includes the step of: overwriting, in the cache memory, the first set of macroblocks with the third set of macroblocks.
Claim 17
Dependent Claim
28 words
The method of claim 12, wherein each set of macroblocks has a size equal to one macroblock and the cache memory has a size equal to two macroblocks.
Claim 18
Dependent Claim
125 words
The method of claim 11, wherein each in the series of reference picture portions corresponds to one in the series of current picture portions, and wherein the method further includes the steps of, for at least one additional current picture portion in the series of current picture portions: C. loading, while maintaining in the cache memory a previous set of macroblocks that formed a portion of a preceding reference picture portion, a new set of macroblocks in the cache memory, the new and previous sets of macroblocks forming the reference picture portion that corresponds to the at least one additional current picture portion; and D. comparing the at least one additional current picture portion to its corresponding reference picture portion loaded in the cache memory.
Claim 19
Dependent Claim
114 words
The method of claim 14, wherein the cache memory includes a first section and a second section, wherein the at least one additional current picture portion includes a plurality of additional current picture portions, each additional current picture portion having a rank in the plurality of additional current picture portions, and wherein the method further includes the step of: repeating steps C and D for each of the plurality of current picture portions, and wherein step C includes the step of loading the new set of macroblocks in the first section for additional current picture portions having an even rank and in the second section for additional current picture portions having an odd rank.
Claim 20
Independent Claim
167 words
A device for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory capable of storing one of a series of reference picture portions, the device comprising: means for loading a first reference picture portion of the series of reference picture portions into the cache memory, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, and loading, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third sets of macroblocks forming a second reference picture portion; and means for comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 21
Independent Claim
167 words
A device for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory capable of storing one of a series of reference picture portions, the device comprising: means for loading a first reference picture portion of the series of reference picture portions into the cache memory, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, and loading, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third sets of macroblocks forming a second reference picture portion; and means for comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 22
Dependent Claim
47 words
The device of claim 16, wherein the first and third sets of macroblocks are equal in size, and wherein the means for loading the third set of macroblocks includes: means for overwriting, in the cache memory, the first set of macroblocks with the third set of macroblocks.
Claim 23
Dependent Claim
35 words
The device of claim 17, in combination with the cache memory, and wherein each set of macroblocks has a size equal to one macroblock and the cache memory has a size equal to two macroblocks.
Claim 24
Dependent Claim
199 words
The device of claim 16, wherein each current picture portion has a rank that defines its position within the series of current picture portions, wherein the cache memory includes a first section and a second section, and wherein the means for comparing further includes means for comparing a next one of the series of current picture portions to a corresponding next one of the series of reference picture portions, the device further including: means for updating the cache memory to include the next one of the series of reference picture portions that corresponds to the next one of the series of current picture portions to be compared, the means for updating including the means for loading, the means for loading further including means for loading a next set of macroblocks into the first section of the cache memory to form the corresponding next one of the series of reference picture portions when the next one of the current picture portions has an even rank, and into the second section of the cache memory to form the corresponding next one of the series of reference picture portions when the next one of the current picture portions has an odd rank.
Claim 25
Dependent Claim
25 words
The device of claim 19, wherein the next set of macroblocks has a size equal to the size of each of the current picture portions.
Claim 26
Independent Claim
169 words
A device for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory capable of storing one of a series of reference picture portions, the device comprising: loading circuitry that loads a first reference picture portion of the series of reference picture portions into the cache memory, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, and loads, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third set of macroblocks forming a second reference picture portion; and comparing circuitry that compares the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 27
Independent Claim
169 words
A device for comparing a series of current picture portions to a series of reference picture portions in a motion picture compression circuit that includes a cache memory capable of storing one of a series of reference picture portions, the device comprising: loading circuitry that loads a first reference picture portion of the series of reference picture portions into the cache memory, the first reference picture portion including a first set of macroblocks and a second set of macroblocks, and loads, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third set of macroblocks forming a second reference picture portion; and comparing circuitry that compares the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 28
Dependent Claim
50 words
The device of claim 21, wherein the first and third sets of macroblocks are equal in size, and wherein the second loading circuitry that loads the third set of macroblocks includes: overwriting circuitry that overwrites, in the cache memory, the first set of macroblocks with the third set of macroblocks.
Claim 29
Dependent Claim
35 words
The device of claim 22, in combination with the cache memory, and wherein each set of macroblocks has a size equal to one macroblock and the cache memory has a size equal to two macroblocks.
Claim 30
Dependent Claim
199 words
The device of claim 21, wherein each of the series of current picture portions has a rank that defines its position within the series of current picture portions, wherein the cache memory includes a first section and a second section, and wherein the comparing circuitry includes circuitry that compares a next one of the series of current picture portions to a corresponding next one of the series of reference picture portions, the device further including: updating circuitry that updates the cache memory to include the next one of the series of reference picture portions that corresponds to the next one of the series of current picture portions to be compared, the updating circuitry including the loading circuitry, the loading circuitry further including circuitry that loads a next set of macroblocks into the first section of the cache memory to form the corresponding next one of the series of reference picture portions when the next one of the current picture portions has an even rank, and into the second section of the cache memory to form the corresponding next one of the series of reference picture portions when the next one of the current picture portions has an odd rank.
Claim 31
Dependent Claim
25 words
The device of claim 24, wherein the next set of macroblocks has a size equal to the size of each of the current picture portions.
Claim 32
Dependent Claim
181 words
A motion picture compression system for comparing a current picture to a reference picture, the current picture including a series of current picture portions, the reference picture including a series of reference picture portions, the system comprising: a cache memory that is capable of storing one of a series of reference picture portions; means for loading the cache memory with a first reference picture portion of the series of reference picture portions, the first reference picture portion including a first set of macroblocks and a second set of macroblocks; means for loading, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third set of macroblocks forming a second reference picture portion; and means for reading and comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 33
Dependent Claim
181 words
A motion picture compression system for comparing a current picture to a reference picture, the current picture including a series of current picture portions, the reference picture including a series of reference picture portions, the system comprising: a cache memory that is capable of storing one of a series of reference picture portions; means for loading the cache memory with a first reference picture portion of the series of reference picture portions, the first reference picture portion including a first set of macroblocks and a second set of macroblocks; means for loading, while maintaining the second set of macroblocks in the cache memory, a third set of macroblocks in the cache memory so that the third set of macroblocks is overwritten over the first set of macroblocks, and the cache memory includes the second and third sets of macroblocks, the second and third set of macroblocks forming a second reference picture portion; and means for reading and comparing the second reference picture portion loaded in the cache memory to a second current picture portion in the series of current picture portions.
Claim 34
Dependent Claim
35 words
The device of claim 26, wherein the means for loading a third set of macroblocks further includes: means for overwriting the first set of macroblocks with the third set of macroblocks in the cache memory.
References Cited (Backward Citations)
US5083202A
Cited
US5144429A
Cited
US5099325A
Cited
US5206723A
Cited
US5153720A
Cited
US5200820A
Cited
US5315388A
Cited
US5475446A
Cited
US5457481A
Cited
US5561475A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |