Specialized millicode instructions for test PSW validity, load with access test, and character translation assist

Claim 1

In a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode method for testing the validity of a program status word, comprising the steps of: storing a millicode instruction that includes a field specifying a processor state unit register in which said program status word is stored and a field specifying a millicode general register in which a mask is stored indicating those bits in the program status word which are to be zeros if the program status word is valid; fetching said millicode instruction from storage; performing a logical AND operation between correspondingly positioned bits in said program status word and bits in said mask; and performing a hardware check on the status of at least one bit in said program status word other than the correspondingly positioned bits in said program status word.