US5694365A
Expired / Lapsed
US
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Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode
Assignee: Mitsubishi Electric Corp
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Filing: 1997-01-06
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Granted: 1997-12-02
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Expires: 2017-01-06
Abstract
Abstract A DRAM includes a substrate voltage generation unit for generating a substrate voltage having a negative value to be applied to a first node. The substrate voltage generation unit includes a detecting circuit. The detecting circuit includes a first PMOS transistor provided in series between a second node with a ground potential and a third node and a second PMOS transistor, and further includes a third PMOS transistor provided in parallel to the first PMOS transistor. The first and second PMOS transistors have the gates connected to the third node, and the third PMOS transistor has a gate receiving a signal. The detecting circuit is provided between the second node with the ground voltage and the first node, and further includes an NMOS transistor having a gate connected to the third node. The third PMOS transistor receives the signal of the "L" level in the self refresh mode and the signal of the "H" level in the normal mode. As a result, the clamp level of the substrate voltage is greater in the self refresh mode than in the normal mode. More specially, the NMOS transistor is turned on with the greater substrate voltage in the self refresh mode than the normal mode, so that the substrate voltage is increased and the capability of pause refresh is improved. Consequently, the interval of internal /RAS can be increased and power consumption can be reduced in the self refresh mode.
Inventors
- 👤 Jun Nakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:40
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
123 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to output node; wherein said substrate voltage generation means includes detecting means for detecting a potential level of said output node, and voltage generation means for generating said substrate voltage in accordance with the potential level detected by said detecting means, said detecting means causes said voltage generation means to operate when the potential of said output node exceeds a predetermined potential, and said detecting means is responsive to a signal indicating that said special mode is entered for setting said predetermined potential to a level higher than the level in the normal mode.
Claim 2
Dependent Claim
123 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to output node; wherein said substrate voltage generation means includes detecting means for detecting a potential level of said output node, and voltage generation means for generating said substrate voltage in accordance with the potential level detected by said detecting means, said detecting means causes said voltage generation means to operate when the potential of said output node exceeds a predetermined potential, and said detecting means is responsive to a signal indicating that said special mode is entered for setting said predetermined potential to a level higher than the level in the normal mode.
Claim 3
Dependent Claim
161 words
The semiconductor memory device according to claim 1, wherein said detecting means includes a plurality of first transistors connected in series between a first node and a second node, control electrodes of said plurality of first transistors are connected to said second node, said second node has a potential in accordance with the potential of said output node, the potential of said second node is lower than the potential of said first node, said detecting means further includes a second transistor connected in parallel to at least one of said plurality of first transistors, said second transistor is turned on by receiving at its control electrode the signal indicating that said special mode is entered, whereby said predetermined potential is set to a level higher in said special mode than in said normal mode, and said predetermined potential in said special mode and said predetermined potential in said normal mode have the magnitude determined by the number of said first transistors.
Claim 4
Dependent Claim
114 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to an output node; wherein said substrate voltage generation means includes detecting means for detecting a potential level of said output node, and voltage generation means for generating said substrate voltage, said detecting means discharges electrons from said output node when the potential of said output node is lower than a predetermined potential, and said detecting means is responsive to a signal indicating that said special mode is entered for setting said predetermined potential to a level higher than the level in the normal mode.
Claim 5
Dependent Claim
114 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to an output node; wherein said substrate voltage generation means includes detecting means for detecting a potential level of said output node, and voltage generation means for generating said substrate voltage, said detecting means discharges electrons from said output node when the potential of said output node is lower than a predetermined potential, and said detecting means is responsive to a signal indicating that said special mode is entered for setting said predetermined potential to a level higher than the level in the normal mode.
Claim 6
Dependent Claim
161 words
The semiconductor memory device according to claim 3, wherein said detecting means includes a plurality of first transistors connected in series between a first node and a second node, control electrodes of said plurality of first transistors are connected to said second node, said second node has a potential in accordance with the potential of said output node, the potential of said second node is lower than the potential of said first node, said detecting means further includes a second transistor connected in parallel to at least one of said plurality of first transistors, said second transistor is turned on by receiving at its control electrode the signal indicating that said special mode is entered, whereby said predetermined potential is set to a level higher in said special mode than in said normal mode, and said predetermined potential in said special mode and said predetermined potential in said normal mode have the magnitude determined by the number of said first transistors.
Claim 7
Dependent Claim
114 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to an output node; wherein said substrate voltage generation means includes pump means for generating said substrate voltage, ring means for generating a pulse signal for causing said pump means to operate, and ring control means for controlling a frequency of said pulse signal from said ring means, and said ring control means is responsive to a signal indicating that said special mode is entered for applying a potential lower than the potential in the normal mode to an input node of said ring means.
Claim 8
Dependent Claim
114 words
A semiconductor memory device having a normal mode and a special mode, comprising: substrate voltage generation means for generating a substrate voltage having a negative value to be applied to an output node; wherein said substrate voltage generation means includes pump means for generating said substrate voltage, ring means for generating a pulse signal for causing said pump means to operate, and ring control means for controlling a frequency of said pulse signal from said ring means, and said ring control means is responsive to a signal indicating that said special mode is entered for applying a potential lower than the potential in the normal mode to an input node of said ring means.
Claim 9
Dependent Claim
157 words
The semiconductor memory device according to claim 5, wherein said ring control means includes a plurality of first transistors connected in series between said input node of said ring means and a high potential node having a potential greater than that of said input node, control electrodes of said plurality of first transistors are connected to said input node, said ring control means further includes a second transistor connected in parallel to at least one of said plurality of first transistors, said second transistor is turned off by receiving at its control electrode the signal indicating that said special mode is entered, thereby applying in said special mode a potential lower than the potential in said normal mode to said input node, and the potential applied to said input node in said special mode and the potential applied to said input mode in said normal mode have the magnitude determined by the number of said first transistors.
Claim 10
Dependent Claim
126 words
A semiconductor memory device having a normal mode and a special mode, comprising: first substrate voltage generation for generating a first substrate voltage having a negative value to be applied to an output node; second substrate voltage generation means constantly in operation for generating a second substrate voltage having a negative value to be applied to said output node; and third substrate voltage generation means responsive to a control signal controlling internal operation of said semiconductor memory device for generating a third substrate voltage having a negative value to be applied to said output node; wherein said first substrate voltage generation means operates in accordance with a potential level of said output node, and said third substrate voltage generation means stops operation in said special mode.
Claim 11
Dependent Claim
126 words
A semiconductor memory device having a normal mode and a special mode, comprising: first substrate voltage generation for generating a first substrate voltage having a negative value to be applied to an output node; second substrate voltage generation means constantly in operation for generating a second substrate voltage having a negative value to be applied to said output node; and third substrate voltage generation means responsive to a control signal controlling internal operation of said semiconductor memory device for generating a third substrate voltage having a negative value to be applied to said output node; wherein said first substrate voltage generation means operates in accordance with a potential level of said output node, and said third substrate voltage generation means stops operation in said special mode.
Claim 12
Dependent Claim
17 words
The semiconductor memory device according to claim 1, wherein said special mode is a self refresh mode.
Claim 13
Dependent Claim
17 words
The semiconductor memory device according to claim 2, wherein said special mode is a self refresh mode.
Claim 14
Dependent Claim
17 words
The semiconductor memory device according to claim 3, wherein said special mode is a self refresh mode.
Claim 15
Dependent Claim
17 words
The semiconductor memory device according to claim 4, wherein said special mode is a self refresh mode.
Claim 16
Dependent Claim
17 words
The semiconductor memory device according to claim 5, wherein said special mode is a self refresh mode.
Claim 17
Dependent Claim
17 words
The semiconductor memory device according to claim 6, wherein said special mode is a self refresh mode.
Claim 18
Dependent Claim
17 words
The semiconductor memory device according to claim 7, wherein said special mode is a self refresh mode.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
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