Semiconductor integrated circuit device having a test mode for reliability evaluation

Claim 2

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: first internal power supply voltage generating means for generating a first internal power supply voltage to be supplied on a first internal power supply voltage supplying line according to an external power supply voltage supplied from an external power supply voltage supplying line; second internal power supply voltage generating means for generating a second internal power supply voltage to be supplied on a second internal power supply voltage supplying line according to said external power supply voltage; first connecting means provided between said external power supply voltage supplying line and said first internal power supply voltage supplying line; and second connecting means provided between said external power supply voltage supplying line and said second internal power supply voltage supplying line; wherein said first and second internal power supply voltage generating means are inactivated in said test mode and are activated in said normal mode, said first connecting means connects said external power supply voltage supplying line to said first internal power supply voltage supplying line in said test mode and disconnects said external power supply voltage supplying line from said first internal power supply voltage supplying line in said normal mode, and said second connecting means connects said external power supply voltage supplying line to said second internal power supply voltage supplying line in said test mode and disconnects said external power supply voltage supplying line from said second internal power supply voltage supplying line in said normal mode.

Claim 3

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: first internal power supply voltage generating means for generating a first internal power supply voltage to be supplied on a first internal power supply voltage supplying line according to a first external power supply voltage supplied from a first external power supply voltage supplying line; second internal power supply voltage generating means for generating a second internal power supply voltage to be supplied on a second internal power supply voltage supplying line according to said first external power supply voltage supplied from a second external power supply voltage supplying line; first connecting means provided between said first external power supply voltage supplying line and said first internal power supply voltage supplying line; and second connecting means provided between said second external power supply voltage supplying line and said second internal power supply voltage supplying line; wherein said first and second internal power supply voltage generating means are inactivated in said test mode and are activated in said normal mode; said first connecting means connects said first external power supply voltage supplying line to said first internal power supply voltage supplying line in said test mode and disconnects said first external power supply voltage supplying line from said first internal power supply voltage supplying line in said normal mode; said second connecting means connects said second external power supply voltage supplying line to said second internal power supply voltage supplying line in said test mode, and disconnects said second external power supply voltage supplying line form said second internal power supply voltage supplying line in said normal mode; in said test mode, said first external power supply voltage supplying line receives a second external power supply voltage and said second external power supply voltage supplying line receives a third external power supply voltage having a level different from that of said second external power supply voltage; and in said normal mode, said first and second external power supply voltage supplying lines receive said first external power supply voltage.

Claim 4

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: first internal power supply voltage generating means for generating a first internal power supply voltage to be supplied on a first internal power supply voltage supplying line according to a first external power supply voltage supplied from a first external power supply voltage supplying line; second internal power supply voltage generating means for generating a second internal power supply voltage to be supplied on a second internal power supply voltage supplying line according to said first external power supply voltage supplied from a second external power supply voltage supplying line; first connecting means provided between said first external power supply voltage supplying line and said first internal power supply voltage supplying line; and second connecting means provided between said second external power supply voltage supplying line and said second internal power supply voltage supplying line; wherein said first and second internal power supply voltage generating means are inactivated in said test mode and are activated in said normal mode; said first connecting means connects said first external power supply voltage supplying line to said first internal power supply voltage supplying line in said test mode and disconnects said first external power supply voltage supplying line from said first internal power supply voltage supplying line in said normal mode; said second connecting means connects said second external power supply voltage supplying line to said second internal power supply voltage supplying line in said test mode, and disconnects said second external power supply voltage supplying line form said second internal power supply voltage supplying line in said normal mode; in said test mode, said first external power supply voltage supplying line receives a second external power supply voltage and said second external power supply voltage supplying line receives a third external power supply voltage having a level different from that of said second external power supply voltage; and in said normal mode, said first and second external power supply voltage supplying lines receive said first external power supply voltage.

Claim 5

The semiconductor integrated circuit device according to claim 2, wherein said second and third external power supply voltages are applied in said test mode to render a difference between said second external power supply voltage and said first internal power supply voltage equal to that between said third external power supply voltage and said second internal power supply voltage.

Claim 6

The semiconductor integrate circuit device according to claim 2, further comprising third connecting means provided between said first external power supply voltage supplying line and said second external power supply voltage supplying line, wherein said third connecting means disconnects said first external power supply voltage supplying line from said second external power supply voltage supplying line in said test mode and connects said first external power supply voltage supplying line to said second external power supply voltage supplying line in said normal mode.

Claim 7

The semiconductor integrated circuit device according to claim 4, wherein said third connecting means is a transistor.

Claim 8

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: first internal power supply voltage generating means for generating a first internal power supply voltage to be supplied on a first internal power supply voltage supplying line according to an external power supply voltage supplied from an external power supply voltage supplying line; second internal power supply voltage generating means for generating a second internal power supply voltage to be supplied on a second internal power supply voltage supplying line according to said external power supply voltage; first connecting means provided between said external power supply voltage supplying line and said first internal power supply voltage supplying line; second connecting means provided between said external power supply voltage supplying line and an intermediate node; and down-converting means provided between said intermediate node and said second internal power supply voltage supplying line; wherein said first and second internal power supply voltage generating means are inactivated in said test mode and are activated in said normal mode; said first connecting means connects said external power supply voltage supplying line to said first internal power supply voltage supplying line in said test mode and disconnects said external power supply voltage supplying line from said first internal power supply voltage supplying line in said normal mode; said second connecting means connects said external power supply voltage supplying line to said intermediate mode in said test mode and disconnects said external power supply voltage supplying line from said intermediate node in said normal mode; and said down-converting means supplies a voltage down-converted from said external power supply voltage to said second internal power supply voltage supplying line in said test mode.

Claim 9

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: first internal power supply voltage generating means for generating a first internal power supply voltage to be supplied on a first internal power supply voltage supplying line according to an external power supply voltage supplied from an external power supply voltage supplying line; second internal power supply voltage generating means for generating a second internal power supply voltage to be supplied on a second internal power supply voltage supplying line according to said external power supply voltage; first connecting means provided between said external power supply voltage supplying line and said first internal power supply voltage supplying line; second connecting means provided between said external power supply voltage supplying line and an intermediate node; and down-converting means provided between said intermediate node and said second internal power supply voltage supplying line; wherein said first and second internal power supply voltage generating means are inactivated in said test mode and are activated in said normal mode; said first connecting means connects said external power supply voltage supplying line to said first internal power supply voltage supplying line in said test mode and disconnects said external power supply voltage supplying line from said first internal power supply voltage supplying line in said normal mode; said second connecting means connects said external power supply voltage supplying line to said intermediate mode in said test mode and disconnects said external power supply voltage supplying line from said intermediate node in said normal mode; and said down-converting means supplies a voltage down-converted from said external power supply voltage to said second internal power supply voltage supplying line in said test mode.

Claim 10

The semiconductor integrated circuit device according to claim 6, wherein when a level of said first internal power supply voltage is higher than that of said second internal power supply voltage, said down-converting means down-converts said external power supply voltage to render a difference between the voltage down-converted from said external power supply voltage and said second internal power supply voltage equal to a difference between said external power supply voltage and said first internal power supply voltage.

Claim 11

The semiconductor integrated circuit device according to claim 7, wherein said down-converting means is a transistor connected to form a diode.

Claim 12

The semiconductor integrated circuit device according to claim 1, wherein said first and second connecting means are transistors.

Claim 13

The semiconductor integrated circuit device according to claim 2, wherein said first and second connecting means are transistors.

Claim 14

The semiconductor integrated circuit device according to claim 6, wherein said first and second connecting means are transistors.

Claim 15

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines each arranged corresponding to each of the rows and each having corresponding said memory cells connected thereto; a plurality of driver means each provided corresponding to each of the word lines; test voltage supplying means for supplying a first test voltage according to an external power supply voltage to each of said driver means via a voltage supplying line in said test mode; and boosted voltage generating means for generating a boosted voltage and supplying said boosted voltage to said driver means in said normal mode; wherein in said normal mode, said driver means corresponding to a selected said word line applies a voltage to the corresponding said word line according to said boosted voltage, and in said test mode, each said driver means applies a voltage to a corresponding said word line according to said first test voltage, and wherein said test voltage supplying means includes current limiting means for limiting a current flowing into said voltage supplying line.

Claim 16

A semiconductor integrated circuit device having a test mode for reliability evaluation and a normal mode, said semiconductor integrated circuit device comprising: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of word lines each arranged corresponding to each of the rows and each having corresponding said memory cells connected thereto; a plurality of driver means each provided corresponding to each of the word lines; test voltage supplying means for supplying a first test voltage according to an external power supply voltage to each of said driver means via a voltage supplying line in said test mode; and boosted voltage generating means for generating a boosted voltage and supplying said boosted voltage to said driver means in said normal mode; wherein in said normal mode, said driver means corresponding to a selected said word line applies a voltage to the corresponding said word line according to said boosted voltage, and in said test mode, each said driver means applies a voltage to a corresponding said word line according to said first test voltage, and wherein said test voltage supplying means includes current limiting means for limiting a current flowing into said voltage supplying line.

Claim 17

The semiconductor integrated circuit device according to claim 12, wherein said current limiting means includes a constant-current source for generating a constant-current and current mirror means.

Claim 18

The semiconductor integrated circuit device according to claim 12, further comprising a plurality of pairs of bit lines each arranged corresponding to each of the rows and each having said memory cells of a corresponding row connected thereto, said each memory cell including: a memory cell transistor; and a memory cell capacitor; wherein a control electrode of said memory cell transistor is connected a corresponding said word line, a first electrode of said memory cell transistor is connected to a corresponding bit line of a corresponding one of said pairs of bit lines, and a second electrode of said memory cell transistor is connected to one end of said memory cell capacitor; and in said test mode, the other end of said memory cell capacitor receives a second test voltage and each of said pairs of bit lines receives a ground voltage.

Claim 19

The semiconductor integrated circuit device according to claim 14, further comprising: a plurality of sense amplifiers provided each corresponding to each of said pairs of bit lines for amplifying a potential difference between bit lines of a corresponding pair of bit lines; equalizing/precharging means for setting each of said pairs of bit lines to a predetermined potential; and sense amplifier controlling means for stopping operation of each of said sense amplifiers in said test mode; wherein said equalizing/precharging means sets said each of said pairs of bit lines to a ground potential in said test mode.