Patent US5694085A successfully refreshed from Google Patents.
US5694085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-power amplifier using parallel transistors
Assignee: Quarterhill Inc
•
Filing: 1996-02-14
•
Granted: 1997-12-02
•
Expires: 2016-02-14
Abstract
Abstract An input radio frequency signal to be amplified is fed to the gate terminals of parallel field effect power transistors through impedance matching networks that comprise parallel resistor-capacitor combinations. The capacitor is selected so that it is self-resonant at the frequency of operation, thereby preventing attenuation of the input signal at that frequency. A shunt resistor is coupled between the gates of the parallel transistors to eliminate odd mode oscillations.
Inventors
- 👤 Mark A. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:39
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/211; H03F3/189; H03F3/19; H03F3/193
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
An amplifier circuit for amplifying an input signal comprising: a pair of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminal, wherein the first terminals of each transistor of the pair of transistors are coupled together; a pair of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the pair being disposed between and in series with the control terminal of one of the transistors of the pair of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below a frequency of interest, while allowing input signals at the frequency of interest to reach the transistor substantially unattenuated; and a bypass resistor coupled between the control terminals of the pair of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.
Claim 2
Dependent Claim
168 words
An amplifier circuit for amplifying an input signal comprising: a pair of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminal, wherein the first terminals of each transistor of the pair of transistors are coupled together; a pair of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the pair being disposed between and in series with the control terminal of one of the transistors of the pair of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below a frequency of interest, while allowing input signals at the frequency of interest to reach the transistor substantially unattenuated; and a bypass resistor coupled between the control terminals of the pair of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.
Claim 3
Dependent Claim
28 words
The amplifier of claim 1, wherein the bypass resistor has a resistance selected to be approximately two to ten times an input impedance of the pair of transistors.
Claim 4
Dependent Claim
12 words
The amplifier of claim 1, wherein the pair of transistors are MOSFETs.
Claim 5
Dependent Claim
32 words
The amplifier of claim 1, wherein the input signal has a fundamental frequency and wherein the capacitor of the parallel matching networks is self-resonant at the fundamental frequency of the input signal.
Claim 6
Dependent Claim
168 words
An amplifier circuit for amplifying an input signal comprising; a plurality of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminals, wherein the first terminals of each transistor of the plurality of transistors are coupled together; a plurality of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the plurality of parallel matching networks being disposed between and in series with a control terminal of one of the plurality of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below the frequency of interest, while allowing the input signal to reach the transistor substantially unattenuated; and a bypass resistor coupled between the control terminals of each transistor of the plurality of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.
Claim 7
Dependent Claim
168 words
An amplifier circuit for amplifying an input signal comprising; a plurality of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminals, wherein the first terminals of each transistor of the plurality of transistors are coupled together; a plurality of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the plurality of parallel matching networks being disposed between and in series with a control terminal of one of the plurality of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below the frequency of interest, while allowing the input signal to reach the transistor substantially unattenuated; and a bypass resistor coupled between the control terminals of each transistor of the plurality of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.
References Cited (Backward Citations)
US3471796A
Cited
US5420537A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |