Patent US5692167A successfully refreshed from Google Patents.
US5692167A
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Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
Assignee: Intel Corp
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Filing: 1996-08-19
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Granted: 1997-11-25
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Expires: 2016-08-19
Abstract
Abstract An apparatus and method for improving the performance of pipelined computer processors which have segment bits for specifying the operand size, the address size for memory reference, and the stack size, and which can run self-modifying code. The processor predicts segment bits based on previously used segment bits. Actual segment bits are later determined during execution of an instruction. The predicted segment bits are compared with the actual segment bits, and the pipeline is flushed if they do not match. Also, an instruction verification method is provided to determine if self-modifying code has modified instructions already in the pipeline. Upon execution of a write instruction, each instruction address in the pipeline is compared with the write address. If a match is found, the pipeline is flushed.
Inventors
- 👤 Edward T. Grochowski
- 👤 Donald B. Alpert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:56
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30192; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/3812; G06F9/3861; G06F9/3867
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
131 words
A method for processing self-modifying code in a pipelined computer processor having a plurality of stages for simultaneously processing a stream of instructions in a pipeline, comprising the steps of: (a) executing an in order write instruction in an execution stage to write data to a write address; (b) comparing the write address with an address of each instruction in the pipeline that is subsequent to said write instruction to determine if the write address matches any of said addresses; (c) if said comparisons do not find a match, then continuing operation; and (d) if any of said comparisons find a match, then performing the steps of flushing each of said instructions in the pipeline following the write instruction, and pre-fetching the locations of said flushed instructions for decoding and execution.
Claim 2
Independent Claim
131 words
A method for processing self-modifying code in a pipelined computer processor having a plurality of stages for simultaneously processing a stream of instructions in a pipeline, comprising the steps of: (a) executing an in order write instruction in an execution stage to write data to a write address; (b) comparing the write address with an address of each instruction in the pipeline that is subsequent to said write instruction to determine if the write address matches any of said addresses; (c) if said comparisons do not find a match, then continuing operation; and (d) if any of said comparisons find a match, then performing the steps of flushing each of said instructions in the pipeline following the write instruction, and pre-fetching the locations of said flushed instructions for decoding and execution.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein, in step (b), a match is determined if the write address is within a predetermined number of bytes from any of the instruction addresses in the pipeline.
Claim 4
Dependent Claim
23 words
The method of claim 1, wherein following said steps (a) and (b), the write instruction completes execution before said steps (c) and (d).
Claim 5
Independent Claim
156 words
A method for processing a stream of instructions in a pipelined computer including branch prediction and segmented memory, including the steps of: a) predicting a branch address to an undetermined memory segment; b) prefetching at least one predicted instruction at said branch address; c) predicting segment bits of said predicted instruction to be the same as the segment bits associated with the branch instruction immediately preceding the predicted instruction; d) decoding said predicted instruction using said predicted segment bits; e) during execution of said branch instruction, determining actual segment bits for said predicted code; and f) comparing said actual segment bits with said predicted segment bits, and performing the steps of if said actual segment bits are equivalent to said predicted segment bits, then continuing operation, and if said actual segment bits are not equivalent to said predicted segment bits, then flushing the pipeline and re-decoding and re-executing said predicted code using said actual segment bits.
Claim 6
Independent Claim
156 words
A method for processing a stream of instructions in a pipelined computer including branch prediction and segmented memory, including the steps of: a) predicting a branch address to an undetermined memory segment; b) prefetching at least one predicted instruction at said branch address; c) predicting segment bits of said predicted instruction to be the same as the segment bits associated with the branch instruction immediately preceding the predicted instruction; d) decoding said predicted instruction using said predicted segment bits; e) during execution of said branch instruction, determining actual segment bits for said predicted code; and f) comparing said actual segment bits with said predicted segment bits, and performing the steps of if said actual segment bits are equivalent to said predicted segment bits, then continuing operation, and if said actual segment bits are not equivalent to said predicted segment bits, then flushing the pipeline and re-decoding and re-executing said predicted code using said actual segment bits.
Claim 7
Dependent Claim
45 words
The method of claim 4, wherein said segment bits specify one of at least two data sizes for operands, address modes, and stack pointers, said data sizes including a first data size of a first length and a second data size of a second length.
Claim 8
Dependent Claim
37 words
The method of claim 4 wherein the segment bits include a segment bit to define operand size of the instruction associated therewith, so that said step (c) includes decoding the first instruction with a predicted operand size.
Claim 9
Dependent Claim
40 words
The method of claim 4 wherein the segment bits include a segment bit to define address size for memory references by the instruction associated therewith, so that said step (c) includes decoding the first instruction with a predicted address size.
Claim 10
Dependent Claim
37 words
The method of claim 4 wherein the segment bits include a segment bit to define stack size for the instruction associated therewith, so that said step (c) includes decoding the first instruction with a predicted stack size.
Claim 11
Dependent Claim
44 words
The method of claim 4 wherein the segment bits include a code segment bit to define operand size and address size for the instruction associated therewith, so that said step (c) includes decoding the first instruction with a predicted operand size and address size.
Claim 12
Dependent Claim
40 words
The method of claim 9 wherein the segment bits further include a stack segment bit to define stack size for the instruction associated therewith, so that said step (c) further includes decoding the first instruction with a predicted stack size.
Claim 13
Dependent Claim
40 words
The verification method of claim 4 including following said step (e), storing the actual segment bits in a segment register file; and said step (f) includes comparing the segment bits in the segment register file with the predicted segment bits.
Claim 14
Dependent Claim
233 words
A computer circuit for handling branch predictions in an instruction code that allows self-modifying code in a pipelined microprocessor having a prefetch stage for fetching and buffering instruction code lines from a computer memory, a decode stage coupled to the prefetch stage for receiving instruction code and decoding it into one or more instructions, and an execution stage, said microprocessor having a segmented memory, comprising: a branch prediction circuit for predicting a branch address responsive to a branch instruction; a segment prediction circuit for predicting segment bits for a predicted instruction; a branch instruction execution circuit in said execution stage for determining an actual target address and actual segment bits responsive to a branch instruction; segment register files holding actual segment bits received from said branch execution circuit; segment bit comparators for comparing predicted segment bits with the actual segment bits from the segment register file; a write address circuit, responsive to a write instruction in said execution stage, for supplying a write destination address; instruction pointer registers for holding current addresses of the instructions in prefetch stage, the decode stage, and the execution stage; write address comparators for comparing the addresses in said instruction pointer registers with said write destination address; and address control means, responsive to said address comparators and said segment bit comparators, for either continuing processing the instructions currently in said pipeline, or selecting an address to be prefetched.
Claim 15
Dependent Claim
233 words
A computer circuit for handling branch predictions in an instruction code that allows self-modifying code in a pipelined microprocessor having a prefetch stage for fetching and buffering instruction code lines from a computer memory, a decode stage coupled to the prefetch stage for receiving instruction code and decoding it into one or more instructions, and an execution stage, said microprocessor having a segmented memory, comprising: a branch prediction circuit for predicting a branch address responsive to a branch instruction; a segment prediction circuit for predicting segment bits for a predicted instruction; a branch instruction execution circuit in said execution stage for determining an actual target address and actual segment bits responsive to a branch instruction; segment register files holding actual segment bits received from said branch execution circuit; segment bit comparators for comparing predicted segment bits with the actual segment bits from the segment register file; a write address circuit, responsive to a write instruction in said execution stage, for supplying a write destination address; instruction pointer registers for holding current addresses of the instructions in prefetch stage, the decode stage, and the execution stage; write address comparators for comparing the addresses in said instruction pointer registers with said write destination address; and address control means, responsive to said address comparators and said segment bit comparators, for either continuing processing the instructions currently in said pipeline, or selecting an address to be prefetched.
Claim 16
Dependent Claim
42 words
The computer circuit of claim 12 further comprising: a pipeline control circuit, responsive to said write address comparators and said segment bit comparators, for flushing the pipeline if either said write address comparators match or said segment bit comparators do not match.
Claim 17
Dependent Claim
19 words
The computer circuit of claim 12 further comprising a second pipeline, so that the microprocessor has a superscalar architecture.
Claim 18
Dependent Claim
61 words
The computer circuit of claim 12 further comprising: a descriptor table for holding descriptor data that describes the data within said segments, said descriptor data including default segment bits indicative of a default data size for a selected segment, the default data sizes including a first data size having a first length and a second data size having a second length.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-24 | 2001-05-26 | 2001-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-24 | 2005-05-26 | 2005-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-24 | 2009-05-26 | 2009-11-25 | $7700.00 | Window Closed / Lapsed |