US5692147A
Expired / Lapsed
US
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Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows by selectively transposing X and Y address portions, and programmable gate array applications thereof
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1997-11-25
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Expires: 2015-06-07
Abstract
Abstract A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.
Inventors
- 👤 Wendell Ray Larsen
- 👤 Frank Ray Keyser
- 👤 Brian A. Worth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
122 words
In a computing system having a plurality of addressable memory units and a plurality of controllable resources arranged in a two-dimensional array, individual ones of the plurality of controllable resources having an associated one of the plurality of memory units corresponding thereto, the plurality of memory units having an N-bit address associated therewith, a method for associating the plurality of memory units to the plurality of controllable resources comprising: using first, second and third portions of the N-bit address, the first and third portions each being switchably associated with a respective one of the two dimensions of the two-dimensional array, the second portion being employed for determining which of the two dimensions each of the first and third portions is associated with.
Claim 2
Dependent Claim
122 words
In a computing system having a plurality of addressable memory units and a plurality of controllable resources arranged in a two-dimensional array, individual ones of the plurality of controllable resources having an associated one of the plurality of memory units corresponding thereto, the plurality of memory units having an N-bit address associated therewith, a method for associating the plurality of memory units to the plurality of controllable resources comprising: using first, second and third portions of the N-bit address, the first and third portions each being switchably associated with a respective one of the two dimensions of the two-dimensional array, the second portion being employed for determining which of the two dimensions each of the first and third portions is associated with.
Claim 3
Dependent Claim
97 words
The method of claim 1 wherein at least one of the plurality of programmable resources comprises a plurality of individual programmable resources and the associated at least one of the plurality of memory units comprises a plurality of individual memory units and wherein individual ones of the plurality of individual programmable resources has a respective one of the plurality of individual memory units corresponding thereto, and wherein the using step further comprises: using a fourth portion of the N-bit address, the fourth portion being employed for addressing the respective one of the plurality of individual memory units.
Claim 4
Dependent Claim
29 words
The method of claim 1 wherein the computing system comprises a field-programmable gate array and wherein the plurality of memory units comprises an SRAM of said field-programmable gate array.
Claim 5
Independent Claim
126 words
A method of allocating memory to a programmable gate array having a plurality of programmable resources addressable per an x,y two-dimensional array, said method comprising steps of: providing a plurality of addressable memory units addressable by an N-bit address, said N-bit address having first, second and third portions; switchably associating the first and third portions of said N-bit address to respective x and y dimensions of the x,y two-dimensional array of the plurality of programmable resources in accordance with the second portion; and allocating memory units of the plurality of addressable memory units as addressed by said N-bit address to respective programmable resources of the plurality of programmable resources within the x,y two-dimensional array as addressed by the first and third portions of said N-bit address.
Claim 6
Independent Claim
126 words
A method of allocating memory to a programmable gate array having a plurality of programmable resources addressable per an x,y two-dimensional array, said method comprising steps of: providing a plurality of addressable memory units addressable by an N-bit address, said N-bit address having first, second and third portions; switchably associating the first and third portions of said N-bit address to respective x and y dimensions of the x,y two-dimensional array of the plurality of programmable resources in accordance with the second portion; and allocating memory units of the plurality of addressable memory units as addressed by said N-bit address to respective programmable resources of the plurality of programmable resources within the x,y two-dimensional array as addressed by the first and third portions of said N-bit address.
Claim 7
Dependent Claim
142 words
A method according to claim 4, wherein a programmable resource of the plurality of programmable resources at a given location of the x,y two dimensional array has a plurality of individual programmable resources addressable along a third z dimension; wherein the N-bit address comprises a fourth portion and wherein said step of using further comprises using said fourth portion of said N-bit address; said method further comprising a step of associating the fourth portion of said N-bit address to the third z dimension of the plurality of individual programmable resources; and wherein said step of allocating includes allocating memory units as addressed by said N-bit address to respective individual programmable resources of said plurality of individual programmable resources along the third z dimension at said given location of the x,y two-dimensional array as addressed by the fourth portion of said N-bit address.
Claim 8
Dependent Claim
117 words
A method according to claim 4, wherein the plurality of programmable resources of the programmable gate array includes: electrically controllable resources; and a programmable SRAM having memory cells coupled for driving the respective electrically controllable resources, the memory cells being addressable per an x,y two-dimensional array; wherein said step of allocating includes allocating memory units of the plurality of addressable memory units as addressed by said N-bit address to respective memory cells of the programmable SRAM, the first and third portions of the N-bit address switchably corresponding to respective x and y dimensions of the x,y two-dimensional array, the-correspondence of the first and third portions being switched in accordance with the second portion of said N-bit address.
Claim 9
Dependent Claim
97 words
A method according to claim 6 further comprising the step of: (a) addressing the plurality of addressable memory units with a given N-bit address; (b) addressing the memory cells of the programmable SRAM, using the first and third portions of said given N-bit address to address respective x and y, or y and x, dimensions of the x,y two dimensional array in accordance with the second portion of said given N-bit address; and (c) transferring data of said addressed memory unit of the plurality of addressable memory units to said addressed memory cell of the programmable SRAM.
Claim 10
Dependent Claim
36 words
A method according to claim 7 further comprising the steps of repeating steps a, b and c, a plurality of times with different N-bit addresses until having programmed all the memory cells of the programmable SRAM.
Claim 11
Dependent Claim
18 words
A method according to claim 6, wherein the electrically controllable resources include configurable logic resources and wiring resources.
Claim 12
Dependent Claim
102 words
A computing system comprising: a plurality of programmable resources addressable per an x,y two-dimensional array; a plurality of addressable memory units addressable per an N-bit address; means for addressing the plurality of addressable memory units per a given N-bit address; means for using first, second and third portions of said N-bit address; and means for switchably addressing respective x and y addressable dimensions of the x,y two-dimensional array of the plurality of programmable resources with the first and third, or the third and first, portions respectfully of said given N-bit address in accordance with the second portion of said given N-bit address.
Claim 13
Dependent Claim
102 words
A computing system comprising: a plurality of programmable resources addressable per an x,y two-dimensional array; a plurality of addressable memory units addressable per an N-bit address; means for addressing the plurality of addressable memory units per a given N-bit address; means for using first, second and third portions of said N-bit address; and means for switchably addressing respective x and y addressable dimensions of the x,y two-dimensional array of the plurality of programmable resources with the first and third, or the third and first, portions respectfully of said given N-bit address in accordance with the second portion of said given N-bit address.
Claim 14
Dependent Claim
18 words
A computing system according to claim 10, wherein said plurality of programmable resources comprises a programmable gate array.
Claim 15
Dependent Claim
86 words
A computing system according to claim 11, wherein said programmable gate array includes: electrically controllable resources; and a programmable SRAM having memory cells coupled for driving the respective electrically controllable resources, the memory cells being addressable per an x,y two-dimensional array; wherein said means for switchably addressing addresses respective x and y addressable dimensions of the programmable SRAM with the first and third, or the third and first, portions respectfully of said given N-bit address in accordance with the second portion of said given N-bit address.
Claim 16
Dependent Claim
52 words
A computing system according to claim 12 further comprising means for transferring data of a memory unit of the plurality of addressable memory units, as addressed per said given N-bit address, to a memory cell of said programmable SRAM, as addressed, per the first and third portions of said given N-bit address.
Claim 17
Dependent Claim
28 words
A computing system according to claim 13 further comprising means for generating a sequence of N-bit addresses so that all memory cells-of said programmable SRAM may be programmed.
Claim 18
Dependent Claim
83 words
A computing system according to claim 10, wherein a programmable resource of the plurality of programmable resources at a given location of the x,y two dimensional array has a plurality of individual programmable resources addressable along a third z dimension; said using means includes means for using a fourth portion of said given N-bit address; and said addressing means includes means for addressing the addressable third z dimension of said plurality of programmable resources per the fourth portion of said given N-bit address.
Claim 19
Dependent Claim
18 words
A computing system according to claim 15, wherein said plurality of programmable resources comprises a programmable gate array.
Claim 20
Dependent Claim
177 words
An improved computing system having: a field programmable gate array including a plurality of programmable resources addressable per respective x and y addresses of an x,y two-dimensional array; memory means including a plurality of memory units for storing configuration data of the field programmable gate array, the plurality of memory units being addressable per an N-bit address, the programmable resources of the plurality of programmable resources being associated with respective memory units of the plurality of memory units; and address means for addressing a programmable resource and a respective memory unit simultaneously for enabling transfer of configuration data from the memory unit to its associated programmable resource; wherein the improvement comprises means within the address means for dividing the N-bit address of the plurality of memory units into using first, second and third portions of the N-bit address, including means for using said first and third portions interchangeably, as a function of a value stored in said second portion, as the x and y, or y and x, addresses respectively for addressing the plurality of programmable resources.
Claim 21
Dependent Claim
177 words
An improved computing system having: a field programmable gate array including a plurality of programmable resources addressable per respective x and y addresses of an x,y two-dimensional array; memory means including a plurality of memory units for storing configuration data of the field programmable gate array, the plurality of memory units being addressable per an N-bit address, the programmable resources of the plurality of programmable resources being associated with respective memory units of the plurality of memory units; and address means for addressing a programmable resource and a respective memory unit simultaneously for enabling transfer of configuration data from the memory unit to its associated programmable resource; wherein the improvement comprises means within the address means for dividing the N-bit address of the plurality of memory units into using first, second and third portions of the N-bit address, including means for using said first and third portions interchangeably, as a function of a value stored in said second portion, as the x and y, or y and x, addresses respectively for addressing the plurality of programmable resources.
Claim 22
Dependent Claim
76 words
A computing system according to claim 17, wherein a programmable resource of the plurality of programmable resources at a given x and y address of the x,y two-dimensional array includes a plurality of individual programmable resources addressable per a third z address; and wherein said address means includes means for using a fourth portion of the N-bit address and employing said fourth portion as said third z address for addressing the plurality of individual programmable resources.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-24 | 2001-05-26 | 2001-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-24 | 2005-05-26 | 2005-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-24 | 2009-05-26 | 2009-11-25 | $7700.00 | Window Closed / Lapsed |