US5477494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for generating address bit patterns for testing semiconductor memory devices
Assignee: Yokogawa Electric Corp
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Filing: 1993-05-25
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Granted: 1995-12-19
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Expires: 2013-05-25
Abstract
Abstract An apparatus for testing a semiconductor memory device even of such a complicated addressing scheme that column address allocation differs from one to another row address. Memory cells of the memory device can be accessed in a desired sequence by changing over the conditions for address translation on a real-time basis. A pattern generator generates a plurality of addresses. A plurality of address bit selector circuits select optionally the addresses outputted from the pattern generator on a bit-by-bit basis. A plurality of switching circuits are provided for changing over a plurality of selected addresses outputted from the address bit selector circuits on a real-time basis. A plurality of address translation/memory circuits are supplied with a plurality of the addresses changed over by the switching circuits. A memory incorporated in each of address translation/memory circuits is divided into a plurality of memory areas selectable on a real-time basis. With the selected addresses switched in response to an address switching signal supplied from the pattern generator, address translation data stored in the memory areas selected by the address switching signal are read out and supplied to the semiconductor memory device under test for accessing memory cells thereof.
Inventors
- 👤 Tadatoshi Miyagawa
- 👤 Yasumitsu Tsutsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
405 words
An apparatus for generating address bit patterns to be provided to a semiconductor memory device under test, the apparatus comprising: a pattern generator for outputting a plurality of address signals on a bit-by-bit basis and for outputting an address switching signal; a plurality of X-address bit selector circuits, each X-address bit selector circuit for receiving the address signals from the pattern generator, arbitrarily selecting X-address data based on the received address signals on a bit-by-bit basis, and outputting the selected X-address data; a plurality of Y-address bit selector circuits, each Y-address bit selector circuit for receiving the address signals from the pattern generator, arbitrarily selecting Y-address data based on the received address signals on a bit-by-bit basis, and outputting the selected Y-address data; an X-address switching circuit for receiving the address switching signal from the pattern generator and the selected X-address data from each X-address bit selector circuit, switching the received X-address data on a real time basis based on the address switching signal, and outputting the switched X-address data; a Y-address switching circuit for receiving the address switching signal from the pattern generator and the selected Y-address data from each Y-address bit selector circuit, switching the received Y-address data on a real time basis based on the address switching signal, and outputting the switched Y-address data; an X-address translation / memory circuit having a memory divided into a plurality of memory areas selectable on a real-time basis, the X-address translation / memory circuit for receiving the address switching signal from the pattern generator and the switched X-address data from the X-address switching circuit, storing the received X-address data in the memory areas, reading from the memory the stored X-address data based on the address switching signal, and outputting the memory X-address data; and a Y-address translation / memory circuit having a memory divided into a plurality of memory areas selectable on a real-time basis, the Y-address translation / memory circuit for receiving the address switching signal from the pattern generator and the switched Y-address data from the Y-address switching circuit, storing the received Y-address data in the memory areas, reading from the memory the stored Y-address data based on the address switching signal, and outputting the memory Y-address data; wherein the outputted memory X-address data and memory Y-address data are respectively supplied to X-address terminals and Y-address terminals of the semiconductor memory device under test for accessing memory cells within the semiconductor memory device.
Claim 2
Independent Claim
405 words
An apparatus for generating address bit patterns to be provided to a semiconductor memory device under test, the apparatus comprising: a pattern generator for outputting a plurality of address signals on a bit-by-bit basis and for outputting an address switching signal; a plurality of X-address bit selector circuits, each X-address bit selector circuit for receiving the address signals from the pattern generator, arbitrarily selecting X-address data based on the received address signals on a bit-by-bit basis, and outputting the selected X-address data; a plurality of Y-address bit selector circuits, each Y-address bit selector circuit for receiving the address signals from the pattern generator, arbitrarily selecting Y-address data based on the received address signals on a bit-by-bit basis, and outputting the selected Y-address data; an X-address switching circuit for receiving the address switching signal from the pattern generator and the selected X-address data from each X-address bit selector circuit, switching the received X-address data on a real time basis based on the address switching signal, and outputting the switched X-address data; a Y-address switching circuit for receiving the address switching signal from the pattern generator and the selected Y-address data from each Y-address bit selector circuit, switching the received Y-address data on a real time basis based on the address switching signal, and outputting the switched Y-address data; an X-address translation / memory circuit having a memory divided into a plurality of memory areas selectable on a real-time basis, the X-address translation / memory circuit for receiving the address switching signal from the pattern generator and the switched X-address data from the X-address switching circuit, storing the received X-address data in the memory areas, reading from the memory the stored X-address data based on the address switching signal, and outputting the memory X-address data; and a Y-address translation / memory circuit having a memory divided into a plurality of memory areas selectable on a real-time basis, the Y-address translation / memory circuit for receiving the address switching signal from the pattern generator and the switched Y-address data from the Y-address switching circuit, storing the received Y-address data in the memory areas, reading from the memory the stored Y-address data based on the address switching signal, and outputting the memory Y-address data; wherein the outputted memory X-address data and memory Y-address data are respectively supplied to X-address terminals and Y-address terminals of the semiconductor memory device under test for accessing memory cells within the semiconductor memory device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |