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US5691573A Expired / Lapsed US ⏱️ 0.0 years remaining

Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines

Assignee: Advanced Micro Devices Inc
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Filing: 1995-06-07
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Granted: 1997-11-25
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Expires: 2015-06-07
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Abstract

Abstract A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH 4 ) as the silicon (Si) source for silicon dioxide (SiO 2 ), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Inventors

  • 👤 Steven Avanzino
  • 👤 Darrell M. Erb
  • 👤 Robin Cheung
  • 👤 Rich Klein

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/01; H10W20/071; H10W20/072; H10W20/45; H10W20/46; H10W20/47; H10W20/48

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 239 words
An integrated circuit semiconductor device having a semiconductor body with a plurality of active devices and multilevel interconnections disposed on the semiconductor body comprising: at least one interconnection level having at least one pair of conductive lines with opposing walls separated by a narrow space of not greater than 0.5 micron and each wall of the pair having a top at a height to establish an aspect ratio of not less than 2 to 1 relative to said narrow space; additional pairs of conductive lines each having opposing walls separated by a space greater than 0.5 micron and each of walls having a top planar with the top of the walls of said one pair; a solid nonconformal insulating material having a dielectric constant of not greater than 4 and being disposed over the top of and along each of the opposing walls of said one pair of conductive lines and bridging the narrow space to enclose, in the narrow space, a void comprising a gaseous insulating material having a dielectric constant of slightly greater than 1, the void in the narrow space being of such a size that the resultant dielectric constant of the combined solid insulating material and the gaseous insulating material in the narrow space is less than 3, said nonconformal insulating material being disposed over the tops of the opposing walls and at least partially in the spaces between the additional pairs of conductive lines.
Claim 2
Dependent Claim 239 words
An integrated circuit semiconductor device having a semiconductor body with a plurality of active devices and multilevel interconnections disposed on the semiconductor body comprising: at least one interconnection level having at least one pair of conductive lines with opposing walls separated by a narrow space of not greater than 0.5 micron and each wall of the pair having a top at a height to establish an aspect ratio of not less than 2 to 1 relative to said narrow space; additional pairs of conductive lines each having opposing walls separated by a space greater than 0.5 micron and each of walls having a top planar with the top of the walls of said one pair; a solid nonconformal insulating material having a dielectric constant of not greater than 4 and being disposed over the top of and along each of the opposing walls of said one pair of conductive lines and bridging the narrow space to enclose, in the narrow space, a void comprising a gaseous insulating material having a dielectric constant of slightly greater than 1, the void in the narrow space being of such a size that the resultant dielectric constant of the combined solid insulating material and the gaseous insulating material in the narrow space is less than 3, said nonconformal insulating material being disposed over the tops of the opposing walls and at least partially in the spaces between the additional pairs of conductive lines.
Claim 3
Dependent Claim 58 words
The integrated circuit semiconductor device of claim 1 wherein a thin layer of solid conformal insulating material having a dielectric constant of not greater than 4 and being not greater than 500 Å in thickness is disposed on each of the opposing walls of the conductive lines and is between the wall and the solid nonconformal insulating material.
Claim 4
Dependent Claim 28 words
The integrated circuit semiconductor device of claim 1 wherein the size of the void in the narrow space is at least one-third the volume in the narrow space.
Claim 5
Dependent Claim 35 words
The integrated circuit semiconductor device of claim 1 wherein a spin on glass is disposed on the solid nonconformal insulating material in the spaces between the opposing walls of the additional pairs of conductive lines.
Claim 6
Dependent Claim 16 words
The integrated circuit semiconductor device of claim 4 wherein the spin on glass is a siloxane.
Claim 7
Dependent Claim 24 words
The integrated circuit semiconductor device of claim 1 wherein the conductive line is at least one of the group of aluminum and aluminum alloy.
Claim 8
Dependent Claim 38 words
The integrated circuit semiconductor device of claim 4 wherein a conformal insulating material having a dielectric constant of not greater than 4 and being not greater than 500 Å in thickness is disposed on the spin on glass.
Claim 9
Dependent Claim 239 words
In an integrated circuit semiconductor device having a semiconductor body with a plurality of active devices and multilevel interconnections disposed on the semiconductor body, at least one interconnection level having at least one pair of conductive lines with opposing walls separated by a narrow space of not greater than 0.5 micron and each wall of the pair having a top at a height to establish an aspect ratio of not less than 2 to 1 relative to said narrow space, additional pairs of conductive lines each having opposing walls separated by a space greater than 0.5 micron and each of the walls having a top planar with the top of the walls of said one pair, comprising: a nonconformal insulating material having a dielectric constant of not greater than 4 and being disposed over the top of and along each of the opposing walls of said one pair of conductive lines and bridging the narrow space to enclose, in the narrow space, a void comprising a gaseous insulating material having a dielectric constant of slightly greater than 1, the void the narrow space being of such a size that the resultant dielectric constant of the combined nonconformal insulating material and the gaseous insulating material in the narrow space is less than 3, said nonconformal insulating material being disposed over the tops of the opposing walls and at least partially in the spaces between the additional pairs of conductive lines.
Claim 10
Dependent Claim 239 words
In an integrated circuit semiconductor device having a semiconductor body with a plurality of active devices and multilevel interconnections disposed on the semiconductor body, at least one interconnection level having at least one pair of conductive lines with opposing walls separated by a narrow space of not greater than 0.5 micron and each wall of the pair having a top at a height to establish an aspect ratio of not less than 2 to 1 relative to said narrow space, additional pairs of conductive lines each having opposing walls separated by a space greater than 0.5 micron and each of the walls having a top planar with the top of the walls of said one pair, comprising: a nonconformal insulating material having a dielectric constant of not greater than 4 and being disposed over the top of and along each of the opposing walls of said one pair of conductive lines and bridging the narrow space to enclose, in the narrow space, a void comprising a gaseous insulating material having a dielectric constant of slightly greater than 1, the void the narrow space being of such a size that the resultant dielectric constant of the combined nonconformal insulating material and the gaseous insulating material in the narrow space is less than 3, said nonconformal insulating material being disposed over the tops of the opposing walls and at least partially in the spaces between the additional pairs of conductive lines.
Claim 11
Dependent Claim 56 words
The integrated circuit semiconductor device of claim 8 wherein a thin layer of conformal insulating material having a dielectric constant of not greater than 4 and being not greater than 500 Å in thickness is disposed on each of the opposing walls of the conductive lines and is between the wall and the nonconformal insulating material.
Claim 12
Dependent Claim 28 words
The integrated circuit semiconductor device of claim 8 wherein the size of the void in the narrow space is at least one-third the volume in the narrow space.
Claim 13
Dependent Claim 34 words
The integrated circuit semiconductor device of claim 8 wherein a spin on glass is disposed on the nonconformal insulating material in the spaces between the opposing walls of the additional pairs of conductive lines.
Claim 14
Dependent Claim 16 words
The integrated circuit semiconductor device of claim 11 wherein the spin on glass is a siloxane.
Claim 15
Dependent Claim 24 words
The integrated circuit semiconductor device of claim 8 wherein the conductive line is at least one of the group of aluminum and aluminum alloy.
Claim 16
Dependent Claim 38 words
The integrated circuit semiconductor device of claim 11 wherein a conformal insulating material having a dielectric constant of not greater than 4 and being not greater than 500 Å in thickness is disposed on the spin on glass.

References Cited (Backward Citations)

US5004704A Cited
US5124014A Cited
US5275977A Cited
US5278103A Cited
US5451804A Cited
US5432128A Cited
US5566045A Cited
US5530293A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-11-24 2001-05-26 2001-11-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-11-24 2005-05-26 2005-11-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-11-24 2009-05-26 2009-11-25 $7700.00 Window Closed / Lapsed

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