Wire bondable package design with maxium electrical performance and minimum number of layers

Claim 2

A package substrate for a semiconductor die having core circuits, input-output circuits, a first plurality and a second plurality of power bond pads for the core circuits, a third plurality and a fourth plurality of power bond pads for the input-output circuits, and a plurality of signal bond pads, the package substrate comprising: a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers; the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface; the top surface having a first land for connecting to the first plurality of power bond pads, a second land for connecting to the second plurality of power bond pads, a third land for connecting to the third plurality of power bond pads, a fourth land for connecting to the fourth plurality of power bond pads, and a plurality of traces for connecting to the plurality of signal bond pads; the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors; the first conductive pattern having a first plane and a third plane, the first plane connected to the first land and the plurality of first external connectors, and the third plane connected to the third land and the plurality of third external connectors; the second conductive pattern having a second plane and a fourth plane, the second plane connected to the second land and the plurality of second external connectors, and the fourth plane connected to the fourth land and the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die; and the plurality of signal traces connected to the plurality of signal external connectors.

Claim 3

The package substrate according to claim 1 wherein the first land is a first plurality of segments, the second land is a second plurality of segments, the third land is a third plurality of segments and the fourth land is a fourth plurality of segments, the first, second, third and fourth plurality of segments arranged in a segmented ring, and the die receiving area surrounded by the segmented ring.

Claim 4

The package substrate according to claim 1 wherein the first land is a first plurality of segments and the second land is a second plurality of segments, the first and second plurality of segments arranged in a first segmented ring, the die receiving area surrounded by the first segmented ring, and the third land is a third plurality of segments and the fourth land is a fourth plurality of segments, the third and fourth plurality of segments arranged in a second segmented ring, the first segmented ring concentrically surrounded by the second segmented ring.

Claim 5

The package substrate according to claim 1 wherein the first land is a first plurality of segments and the second land is a second plurality of segments, the first and second plurality of segments arranged in a segmented ring, the die receiving area surrounded by the segmented ring, and the third land and the fourth land are two concentric rings, the segmented ring concentrically surrounded by the two concentric rings.

Claim 6

The package substrate according to claim 1 wherein the first land and the second land are two concentric rings, the die receiving area surrounded by the two concentric rings, and the third land is a first plurality of segments and the fourth land is a second plurality of segments, the first and second plurality of segments arranged in a segmented ring, the two concentric rings concentrically surrounded by the segmented ring.

Claim 7

The package substrate according to claim 1 wherein the first land and the second land are two concentric rings, the die receiving area surrounded by the two concentric rings, and the third land and the fourth land are an other two concentric rings, the first land and the second land concentrically surrounded by the third land and the fourth land.

Claim 8

The package substrate according to claim 1 further comprising: at least one thermal via, the at least one thermal via having one end and an other end, the one end located on the top surface of the package substrate in the die receiving area, the one end adapted to thermally connect to said semiconductor die, and the other end located on the bottom surface of the package substrate, the other end adapted for connection to a thermal sink.

Claim 9

The package substrate according to claim 1 wherein the first, second and third dielectric layers of said package substrate are epoxy.

Claim 10

The package substrate according to claim 1 wherein the first, second and third dielectric layers of said package substrate are polyimide.

Claim 11

The package substrate according to claim 1 wherein the first, second and third dielectric layers of said package substrate are fiberglass reinforced plastic.

Claim 12

The package substrate according to claim 1 wherein the first, second and third dielectric layers of said package substrate are ceramic.

Claim 13

The package substrate according to claim 1 wherein the external connectors are pins.

Claim 14

The package substrate according to claim 1 wherein the external connectors are solder ball bumps.

Claim 15

The package substrate according to claim 1 wherein the third plane encircles the first plane, and the fourth plane encircles the second plane.

Claim 16

A semiconductor device assembly, comprising: a package substrate comprising: a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers; the top surface having a die receiving area, the die receiving area surrounded by a land area, and the land area surrounded by a trace area, the land area having a first land, a second land, a third land, and a fourth land, and the trace area having a plurality of traces; the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors, the plurality of signal external connectors connecting to the plurality of traces; the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface; the first conductive pattern having a first plane and a third plane, the first plane connected to the first land and the plurality of first external connectors, and the third plane connected to the third land and the plurality of third external connectors; the second conductive pattern having a second plane and a fourth plane, the second plane connected to the second land and the plurality of second external connectors, and the fourth plane connected to the fourth land and the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance; and a semiconductor die having core circuits and input-output circuits, said semiconductor die located in the die receiving area on the top surface of said package substrate, said semiconductor die comprising: a plurality of first power bond pads for the core circuits, the plurality of first power bond pads connected to the first land; a plurality of second power bond pads for the core circuits, the plurality of second power bond pads connected to the second land; a plurality of third power bond pads for the input-output circuits, the plurality of third power bond pads connected to the third land; a plurality of fourth power bond pads for the input-output circuits, the plurality of fourth power bond pads connected to the fourth land, thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die; and a plurality of signal bond pads, the plurality of signal bond pads connected to the plurality of traces of said package substrate.

Claim 17

A semiconductor device assembly, comprising: a package substrate comprising: a top surface, a bottom surface, first and second conductive patterns, and first, second and third dielectric layers; the top surface having a die receiving area, the die receiving area surrounded by a land area, and the land area surrounded by a trace area, the land area having a first land, a second land, a third land, and a fourth land, and the trace area having a plurality of traces; the bottom surface having a plurality of first external connectors, a plurality of second external connectors, a plurality of third external connectors, a plurality of fourth external connectors, and a plurality of signal external connectors, the plurality of signal external connectors connecting to the plurality of traces; the first dielectric layer disposed between the top surface and the first conductive pattern, the second dielectric layer disposed between the first and second conductive patterns, and the third dielectric layer disposed between the second conductive pattern and the bottom surface; the first conductive pattern having a first plane and a third plane, the first plane connected to the first land and the plurality of first external connectors, and the third plane connected to the third land and the plurality of third external connectors; the second conductive pattern having a second plane and a fourth plane, the second plane connected to the second land and the plurality of second external connectors, and the fourth plane connected to the fourth land and the plurality of fourth external connectors, the first and second planes positioned in a biplanar relationship for forming an electrical capacitance, and the third and fourth planes positioned in a biplanar relationship for forming an electrical capacitance; and a semiconductor die having core circuits and input-output circuits, said semiconductor die located in the die receiving area on the top surface of said package substrate, said semiconductor die comprising: a plurality of first power bond pads for the core circuits, the plurality of first power bond pads connected to the first land; a plurality of second power bond pads for the core circuits, the plurality of second power bond pads connected to the second land; a plurality of third power bond pads for the input-output circuits, the plurality of third power bond pads connected to the third land; a plurality of fourth power bond pads for the input-output circuits, the plurality of fourth power bond pads connected to the fourth land, thereby decoupling the core circuits of said semiconductor die from the input-output circuits of said semiconductor die; and a plurality of signal bond pads, the plurality of signal bond pads connected to the plurality of traces of said package substrate.

Claim 18

The semiconductor device assembly according to claim 15 wherein the first land is a first plurality of segments, the second land is a second plurality of segments, the third land is a third plurality of segments and the fourth land is a fourth plurality of segments, the first, second, third and fourth plurality of segments arranged in a segmented ring, and the die receiving area surrounded by the segmented ring.

Claim 19

The semiconductor device assembly according to claim 15 wherein the first land is a first plurality of segments and the second land is a second plurality of segments, the first and second plurality of segments arranged in a first segmented ring, the die receiving area surrounded by the first segmented ring, and the third land is a third plurality of segments and the fourth land is a fourth plurality of segments, the third and fourth plurality of segments arranged in a second segmented ring, the first segmented ring concentrically surrounded by the second segmented ring.

Claim 20

The semiconductor device assembly according to claim 15 wherein the first land is a first plurality of segments and the second land is a second plurality of segments, the first and second plurality of segments arranged in a segmented ring, the die receiving area surrounded by the segmented ring, and the third land and the fourth land are two concentric rings, the segmented ring concentrically surrounded by the two concentric rings.

Claim 21

The semiconductor device assembly according to claim 15 wherein the first land and the second land are two concentric rings, the die receiving area surrounded by the two concentric rings, and the third land is a first plurality of segments and the fourth land is a second plurality of segments, the first and second plurality of segments arranged in a segmented ring, the two concentric rings concentrically surrounded by the segmented ring.

Claim 22

The semiconductor device assembly according to claim 15 wherein the first land and the second land are two concentric rings, the die receiving area surrounded by the two concentric rings, and the third land and the fourth land are an other two concentric rings, the first land and the second land concentrically surrounded by the third land and the fourth land.

Claim 23

The semiconductor device assembly according to claim 15 further comprising: at least one thermal via, the at least one thermal via having one end and an other end, the one end located on the top surface of the package substrate in the die receiving area, and the other end located on the bottom surface of the package substrate, the other end adapted for connection to a thermal sink; and a thermally conductive epoxy disposed between the semiconductor die and the one end of the at least one thermal via for conducting heat generated by the semiconductor die to the other end adapted for connection to a thermal sink.