Process of forming channel stopper exactly nested in area assigned to thick field oxide layer

Claim 2

A process of forming an electrical isolation in a semiconductor layer of a first oxidizable material, comprising the steps of: a) forming a laminated structure including at least a first layer of a second oxidizable material and a second layer of an oxygen non-diffusable material over said semiconductor layer; b) patterning said laminated structure into a protection mask against an oxidation atmosphere having a first opening over a first area of said semiconductor layer assigned to a field oxide layer; c) exposing said semiconductor layer covered with said protection mask to an oxidation atmosphere so as to grow said field oxide layer on said first area and an obstacle layer on an inner surface of said first layer, said obstacle layer defining a second opening over a second area nested in said first area; d) ion implanting a dopant impurity through said field oxide layer into said second area by using said protection mask and said obstacle layer as an ion-implantation mask so as to form a channel stopper beneath said field oxide layer; and e) removing said ion-implantation mask from said semiconductor layer so as to leave said field oxide layer and said channel stopper in said semiconductor layer.

Claim 3

The process as set forth in claim 1, in which said second layer has two sub-layers where said first layer is sandwiched, and said laminated structure further includes a pad layer between said semiconductor layer and one of said two sub-layers.

Claim 4

The process as set forth in claim 2, in which a part of said pad layer over said first area is exposed to said first opening.

Claim 5

The process as set forth in claim 3, in which said step b) includes the sub-steps of: b-1) covering the other of said two sub-layers with a photo-resist layer; b-2) transferring a pattern image for said first opening from a reticle to said photo-resist layer; b-3) developing said photo-resist layer into a photo-resist etching mask; and b-4) partially etching said other of said two sub-layers, said first layer and said one of said two sublayers so as to form said first opening.

Claim 6

The process as set forth in claim 1, in which said first oxidizable material, said second oxidizable material and said oxygen non-diffusable material are single crystal silicon, polysilicon and silicon nitride.

Claim 7

The process as set forth in claim 5, in which said laminated structure further includes a pad layer of silicon oxide on said semiconductor layer of said single crystal silicon, and said second layer has two sub-layers for sandwiching said first layer of said polysilicon therebetween, an inner peripheral portion of said first layer and said first area of said semiconductor layer being thermally oxidized by exposing to an oxygen-containing atmosphere.

Claim 8

A process of forming an electrical isolation in a semiconductor layer of an oxidizable material, comprising the steps of: a) forming a laminated structure including a first layer of an oxygen non-diffusable material and a second layer of a material different from said oxygen non-diffusable material between said semiconductor layer and said first layer; b) patterning said laminated structure into an ion-implantation mask having a first opening over a first area of said semiconductor layer assigned to a channel stopper; c) etching an inner peripheral portion of said second layer exposed to said first opening so as to expand a part of said first opening to a second opening over a second area of said semiconductor layer assigned to a field oxide layer, said first area being nested in said second area; d) growing said field oxide layer on said second area by exposing said semiconductor layer covered with said ion-implantation mask to an oxidizing atmosphere; e) ion implanting a dopant impurity through said field oxide layer into said first area so as to form said channel stopper beneath said field oxide layer; and f) removing said ion-implantation mask from said semiconductor layer so as to leave said field oxide layer and said channel stopper in said semiconductor layer.

Claim 9

A process of forming an electrical isolation in a semiconductor layer of an oxidizable material, comprising the steps of: a) forming a laminated structure including a first layer of an oxygen non-diffusable material and a second layer of a material different from said oxygen non-diffusable material between said semiconductor layer and said first layer; b) patterning said laminated structure into an ion-implantation mask having a first opening over a first area of said semiconductor layer assigned to a channel stopper; c) etching an inner peripheral portion of said second layer exposed to said first opening so as to expand a part of said first opening to a second opening over a second area of said semiconductor layer assigned to a field oxide layer, said first area being nested in said second area; d) growing said field oxide layer on said second area by exposing said semiconductor layer covered with said ion-implantation mask to an oxidizing atmosphere; e) ion implanting a dopant impurity through said field oxide layer into said first area so as to form said channel stopper beneath said field oxide layer; and f) removing said ion-implantation mask from said semiconductor layer so as to leave said field oxide layer and said channel stopper in said semiconductor layer.

Claim 10

The process as set forth in claim 7, in which said oxidizable material and said oxygen non-diffusable material are single crystal silicon and silicon nitride.

Claim 11

The process as set forth in claim 8, in which said material for said second layer is polysilicon.

Claim 12

The process as set forth in claim 9, in which said laminated structure further includes a pad layer of silicon oxide between said semiconductor layer and said second layer, and said step b) includes the sub-steps of b-1) covering said first layer with a photo-resist layer, b-2) transferring a pattern image for said first opening from a reticle to said photo-resist layer; b-3) developing said photo-resist layer into a photo-resist etching mask; and b-4) partially etching said first layer and said second layer so as to form said first opening.