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US5689635A
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Microprocessor memory test circuit and method
Assignee: STMicroelectronics lnc USA
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Filing: 1995-12-27
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Granted: 1997-11-18
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Expires: 2015-12-27
Abstract
Abstract A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.
Inventors
- 👤 Gianluca Petrosino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
85 words
A method for testing a plurality of volatile memory cells on a microprocessor for use in an electronic system comprising the steps of: holding a reset line down after a power-up of said microprocessor to disable the electronic system other than the microprocessor until said plurality of volatile memory cells have been tested; testing said plurality of volatile memory cells; replacing a failed memory cell with a redundant memory cell, and, releasing the reset line after said plurality of volatile memory cells have been tested.
Claim 2
Independent Claim
85 words
A method for testing a plurality of volatile memory cells on a microprocessor for use in an electronic system comprising the steps of: holding a reset line down after a power-up of said microprocessor to disable the electronic system other than the microprocessor until said plurality of volatile memory cells have been tested; testing said plurality of volatile memory cells; replacing a failed memory cell with a redundant memory cell, and, releasing the reset line after said plurality of volatile memory cells have been tested.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said step of holding a reset line low is performed using a bi-directional reset line.
Claim 4
Dependent Claim
23 words
The method of claim 1 wherein the step of testing a plurality of volatile memory cells is performed using an on-chip memory circuit.
Claim 5
Dependent Claim
18 words
The method of claim 1 wherein said plurality of volatile memory cells is a plurality of cache memory.
Claim 6
Dependent Claim
16 words
The method of claim 1 wherein said plurality of volatile memory cells comprises a RAM memory.
Claim 7
Dependent Claim
17 words
The method of claim 1 wherein said plurality of volatile memory cells comprises a static RAM memory.
Claim 8
Dependent Claim
63 words
A microprocessor for use in an electronic system comprising: volatile memory having an address bus and a data bus; a test bus in addition to the address bus and data bus of said volatile memory; an on-chip memory test circuit coupled to said test bus; and means for disabling the electronic system other than the microprocessor until said volatile memory had been tested.
Claim 9
Dependent Claim
63 words
A microprocessor for use in an electronic system comprising: volatile memory having an address bus and a data bus; a test bus in addition to the address bus and data bus of said volatile memory; an on-chip memory test circuit coupled to said test bus; and means for disabling the electronic system other than the microprocessor until said volatile memory had been tested.
Claim 10
Dependent Claim
24 words
The microprocessor of claim 7 wherein the on-chip memory test circuit further comprises an input register, a sequencer, an adder, and an output register.
Claim 11
Dependent Claim
13 words
The microprocessor of claim 7 wherein said volatile memory comprises a RAM memory.
Claim 12
Dependent Claim
14 words
The microprocessor of claim 7 wherein said volatile memory comprises a static RAM memory.
Claim 13
Dependent Claim
13 words
The microprocessor of claim 7 wherein said volatile memory comprises a cache memory.
Claim 14
Dependent Claim
46 words
The microprocessor of claim 5 wherein said means for disabling the electronic system other than the microprocessor further comprises: means for holding a reset line down after a power-up of said microprocessor; and means for releasing the reset line after said volatile memory has been tested.
Claim 15
Dependent Claim
19 words
The microprocessor of claim 7 further comprising: means for replacing a failed memory cell with a redundant memory cell.
Claim 16
Dependent Claim
62 words
A microcontroller for use in an electronic system comprising: volatile memory having an address bus and a data bus; a test bus in addition to the address bus and data bus of said volatile memory; an on-chip memory test circuit coupled to said test bus; and means for disabling the electronic system other then microcontroller until said volatile memory has been tested.
Claim 17
Dependent Claim
62 words
A microcontroller for use in an electronic system comprising: volatile memory having an address bus and a data bus; a test bus in addition to the address bus and data bus of said volatile memory; an on-chip memory test circuit coupled to said test bus; and means for disabling the electronic system other then microcontroller until said volatile memory has been tested.
Claim 18
Dependent Claim
24 words
The microcontroller of claim 14 wherein the on-chip memory test circuit further comprises an input register, a sequencer, an adder, and an output register.
Claim 19
Dependent Claim
13 words
The microcontroller of claim 14 wherein said volatile memory comprises a RAM memory.
Claim 20
Dependent Claim
14 words
The microcontroller of claim 14 wherein said volatile memory comprises a static RAM memory.
Claim 21
Dependent Claim
13 words
The microcontroller of claim 14 wherein said volatile memory comprises a cache memory.
Claim 22
Dependent Claim
46 words
The microprocessor of claim 14 wherein said means for disabling the electronic system other than the microcontroller further comprises: means for holding a reset line down after a power-up of said microcontroller; and means for releasing the reset line after said volatile memory has been tested.
Claim 23
Dependent Claim
19 words
The microcontroller of claim 14 further comprising: means for replacing it failed memory cell with a redundant memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |