Method and apparatus for civilian receiver operation with P(Y) code in satellite positioning system receiver

Claim 3

The system of claim 1, wherein said RECEIVING MEANS further comprises: a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals; a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the signal/noise ratio of the received signals L1 and L2; a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1, QL1, IL2, QL2).

Claim 4

The system of claim 2 further comprising a MASTER OSCILLATOR MEANS and a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, conductively connected to said IF PROCESSOR MEANS, conductively connected to said DOWNCONVERTER MEANS, and conductively connected to at least one said DIGITAL CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals.

Claim 5

The system of claim 1, wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises: an L1 DIGITAL CHANNEL PROCESSOR MEANS for tracking L1 C/A code and for tracking L1 P(G) code; and a MICROPROCESSOR MEANS system connected to said L1 DIGITAL CHANNEL PROCESSOR MEANS; wherein said L1 DIGITAL CHANNEL PROCESSING MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and wherein each said L1 DIGITAL CHANNEL PROCESSING MEANS are synchronously clocked by said SCLK signal; said SCLK timing signal being outputted by said FREQUENCY SYNTHESIZER MEANS; and wherein said MICROPROCESSOR MEANS system is fed by output signals from each said L1 DIGITAL CHANNEL PROCESSING MEANS; and wherein each said L1 DIGITAL CHANNEL PROCESSING MEANS is fed by a control signal from said MICROPROCESSOR MEANS.

Claim 6

The system of claim 4, wherein said L1 DIGITAL CHANNEL PROCESSING MEANS further comprises: a carrier numerically controlled oscillator (CARRIER NCO MEANS); a CARRIER MIXER MEANS connected to said CARRIER NCO MEANS for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with, outputted by said CARRIER NCO MEANS, inphase and quadrature components of digital carrier; wherein said CARRIER MIXER MEANS outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency; a CODE MIXER and GENERATOR MEANS connected to said CARRIER MIXER for providing a locally generated replica of C/A code; a CODE MIXER and MEANS connected to said CARRIER MIXER MEANS and connected to said CODE MIXER and GENERATOR MEANS for code-correlating said CARRIER MIXER MEANS output signals with said locally generated replica of C/A code; wherein when said L1 DIGITAL CHANNEL PROCESSING MEANS's carrier tracking loop is closed via said CARRIER NCO MEANS, the input to said CODE MIXER MEANS represents the satellite signal L1 C/A code; and wherein said CODE MIXER MEANS performs said code correlation at 3 time points (early (E), punctual (P), and late (L)) on the autocorrelation function graph creating E, P, and L samples of the autocorrelation function; a block C/A CODE CORRELATORS MEANS connected to said CODE MIXER MEANS for integrating said early, punctual and late samples of said autocorrelation function over an integer multiple of C/A EPOCH signals; wherein said C/A CODE CORRELATORS MEANS outputs early (E), punctusal (P), and late (L) components of said C/A signal in inphase (I) and quadrature (Q) channels (E I C/A, P I C/A, L I C/A, E Q C/A, P Q C/A, L Q C/A) that are fed to said MICROPROCESSOR SYSTEM MEANS at a rate of L1 C/A EPOCH , and wherein said MICROPROCESSOR SYSTEM MEANS uses said C/A CODE CORRELATORS MEANS output signals to facilitate tracking of said C/A signal and to develop feedback signals for the L1 carrier tracking loop and for the L1 code tracking loop; and a P(G) CODE CORRELATORS MEANS connected to said CODE MIXER and GENERATOR MEANS and connected to said C/A CODE CORRELATORS MEANS for generating the signals (E I P(G), P I P(G), L I P(G), E Q P(G), P Q P(G), L Q P(G)) that are read by said MICROPROCESSOR SYSTEM to facilitate tracking of the P(G) signal, and to develop feedback signals for the L1 carrier tracking loop and for the L1 code tracking loop.

Claim 7

The system of claim 5, wherein said CODE MIXER and GENERATOR MEANS further comprises: a CODE NCO MEANS using a sampling clock SCLK for generating a first clocking signal at the P code rate, wherein said first clocking signal can be altered using said MICROPROCESSOR CONTROL signal to facilitate the code tracking; a DIVIDING MEANS connected to said CODE NCO MEANS for dividing said first clocking signal and for generating a second clocking signal at C/A code clocking rate; a C/A CODE GENERATOR MEANS connected to said first DIVIDING MEANS for generating a C/A code signal and a C/A EPOCH signal under the CONTROL signal of said MICROPROCESSOR MEANS, wherein said C/A code signal is the locally generated C/A code used in C/A tracking, and wherein said C/A EPOCH signal is the repetition rate of said C/A code, and wherein said C/A CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite's C/A code; a P CODE GENERATOR MEANS connected to said CODE NCO MEANS, wherein said P CODE GENERATOR MEANS is clocked by said first clocking signal under the CONTROL signal of said MICROPROCESSOR MEANS, and wherein said P CODE GENERATOR generates a P code signal, an X1 signal, and a X1A signal for driving a G CODE GENERATOR; and wherein said P CODE GENERATOR can be adjusted under said CONTROL signal to generate a particular satellite's P code; a W SYNC GENERATOR MEANS connected to said CODE NCO MEANS for dividing said first clocking signal by N, N being an integer, for generating an output signal W Sync , and for synchronizing said W Sync signal to said C/A EPOCH signal; a G CODE GENERATOR connected to said P CODE GENERATOR MEANS and connected to said W SYNC GENERATOR MEANS for generating a G code signal; a CODE MIXER 1 MEANS connected to said P CODE GENERATOR for mixing I inphase (I) and quadrature (Q) versions of an incoming signal with said locally generated P code signal, and for generating inphase and quadrature, early (E), punctual (P), and late (L), versions of the elected satellite's W code signal (I P--EPL and Q P--EPL ); a SUMMER DELAY BLOCK MEANS connected to said CODE MIXER 1 MEANS for further processing said I P--EPL and Q P--EPL signals by integrating said I P--EPL and Q P--EPL signals across the period W Sync , and for delaying said integrated ΣI P--EPL and ΣQ P--EPL signals by a variable integer number K of W Sync periods; and a CODE MIXER 2 MEANS connected to said SUMMER DELAY BLOCK and connected to said G CODE GENERATOR MEANS for mixing said generated delayed and integrated ΣI P--EPL and ΣQ P--EPL signals with said G code signal, and for generating output signals I EPL and Q EPL for further integration in said P(G) CODE CORRELATORS BLOCK.

Claim 8

The system of claim 6, wherein said DIVIDING MEANS connected to said CODE NCO MEANS for dividing said first clocking signal and for generating a second clocking signal at C/A code clocking rate comprises a DIVIDE BY 10 BLOCK.

Claim 9

The system of claim 7, wherein said W SYNC GENERATOR MEANS connected to said CODE NCO MEANS comprises a W SYNC BLOCK for dividing said first clocking signal by 22.

Claim 10

The system of claim 6, wherein said CODE MIXER 1 further comprises: a first MIXER for mixing an inphase (I) component of an incoming signal with an early (E) version of said locally generated P code signal; a second MIXER for mixing an inphase (I) component of an incoming signal with a punctual (P) version of said locally generated P code signal; a third MIXER for mixing an inphase (I) component of an incoming signal with a late (L) version of said locally generated P code signal; wherein an inphase early, an inphase punctual, and an inphase late version I P--EPL represents an inphase version I of the elected satellite's W code signal; and a fourth MIXER for mixing a quadrature (Q) component of an incoming signal with an early (E) version of said locally generated P code signal; a fifth MIXER for mixing a quadrature (Q) component of an incoming signal with a punctual (P) version of said locally generated P code signal; and a sixth MIXER for mixing a quadrature (Q) component of an incoming signal with a late (L) version of said locally generated P code signal; wherein a quadrature early, a quadrature punctual, and a quadrature late versions Q P--EPL represent a quadrature version Q of the elected satellite's W code signal.

Claim 11

The system of claim 6, wherein said SUMMER DELAY BLOCK MEANS further comprises: a DIGITAL SUMMER 1, a DIGITAL SUMMER 2, and a DIGITAL SUMMER 3 for integrating said inphase version I of the elected satellite's W code signal I P--EPL across the period W Sync ; and a DIGITAL DELAY 1, a DIGITAL DELAY 2, and a DIGITAL DELAY 3 for delaying said integrated ΣI P--EPL by a variable integer number of W Sync periods; and a DIGITAL SUMMER 4, a DIGITAL SUMMER 5, and a DIGITAL SUMMER 6 for integrating said quadrature version Q of the elected satellite's W code signal Q P--EPL across the period W Sync ; and a DIGITAL DELAY 4, a DIGITAL DELAY 5, and a DIGITAL DELAY 6 for delaying said integrated ΣQ P--EPL by a variable integer number of W Sync periods.

Claim 12

The system of claim 6, wherein said G CODE GENERATOR further comprises: a W CODE GENERATOR MEANS for generating a W code with an unknown variable underlying clocking rate; a DIGITAL SUMMER MEANS connected to said W CODE GENERATOR MEANS for integrating said W code signal across the period W Sync ; wherein a top bit of said integrated signal forms a G code signal; and wherein said variable underlying clocking rate of said W code signal is masked with said period of W Sync ; said constant period W Sync being equal to the inverse zero-frequency 1/F 0 of the W-code energy spectrum, and wherein said zero-frequency F 0 is the first frequency at which said W-code energy spectrum is equal to zero; and wherein said G code signal comprises a string of `1`s and `0`s at a rate of W Sync clocks; and wherein said W Sync clock signal is synchronized to said C/A EPOCH signal; and a DIGITAL DELAY connected to said DIGITAL SUMMER MEANS for variably delaying said G code by K W.sub. sync clocks in order to prevent the effective transmission of a spoofing signal.

Claim 13

The system of claim 6, wherein said W SYNC GENERATOR MEANS further comprises: a ZERO FREQUENCY F 0 MEANS for multiplying said NCO clocking signal by the zero frequency F 0 of the W-code energy spectrum; wherein said zero-frequency F 0 is the first frequency at which said W-code energy spectrum is equal to zero; and wherein said W SYNC GENERATOR MEANS generates said W Sync clock signal.

Claim 14

The system of claim 12, wherein said ZERO FREQUENCY F 0 MEANS further comprises a DIVIDE BY 22 MEANS; and wherein said W SYNC GENERATOR MEANS generates a 22 P(Y) clock signal; and wherein said W Sync clock signal is synchronized to said C/A EPOCH signal.

Claim 15

The system of claim 6, wherein said CODE MIXER 2 further comprises: a first MIXER BLOCK for mixing said delayed and integrated inphase ΣI P--EPL signals with said G code signal, and for generating output signals I EPL for further integration in said P(G) CODE CORRELATORS BLOCK; and a second MIXER BLOCK for mixing said delayed and integrated quadrature ΣQ P--EPL signals with said G code signal, and for generating output signals Q EPL for further integration in said P(G) CODE CORRELATORS BLOCK.

Claim 16

The system of claim 10, wherein said DIGITAL SUMMER MEANS further comprises: an ADDER MEANS for inputting an input signal SIGNAL IN ; a LATCH 1 MEANS connected to said ADDER 1 MEANS, wherein said W Sync signal clears said LATCH 1 for preparation for the next accumulation; and wherein said LATCH 1 and said ADDER perform the accumulation of said input signal SIGNAL IN over the period of W Sync signal; a LATCH 2 MEANS connected to said LATCH 1 MEANS and connected to said ADDER 1 MEANS for latching in said W Sync signal; and a COMPARATOR connected to said LATCH 2 MEANS for producing an output W out signal; wherein said W out signal is equal to the MSB (most significant bit of the input signal accumulation Σ(SIGNAL IN ) over the period of a W Sync signal.

Claim 17

The system of claim 10, wherein said DIGITAL DELAY MEANS further comprises: a SHIFT REGISTER MEANS for delaying an input signal by an integer number M of W Sync clocks; and a MULTIPLEXER MEANS connected to said SHIFT REGISTER MEANS for selecting said integer number M under a CONTROL signal.