US5688706A
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Method for fabricating a MOSFET device, with local channel doping, self aligned to a selectively deposited tungsten gate
Assignee: Vanguard International Semiconductor Corp
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Filing: 1996-08-01
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Granted: 1997-11-18
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Expires: 2016-08-01
Abstract
Abstract A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the local, narrow threshold voltage adjust region, self aligned to an overlying, narrow tungsten-polysilicon gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Selective deposition of tungsten results in the creation of a tungsten gate structure, in the narrow hole opening, on the top surface of the polysilicon layer. Patterning of the polysilicon layer, using the overlying tungsten gate structure as a mask, results in an polysilicon gate structure, underlying the tungsten gate structure, in the narrow hole opening. The composite narrow tungsten-polysilicon gate structure is self aligned to the underlying, local, narrow threshold voltage adjust region.
Inventors
- 👤 Horng-Huei Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D30/0217; H10D30/60; H10D30/601
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
285 words
A method of fabricating a MOSFET device, on a semiconductor substrate, with a narrow metal-polysilicon gate structure, self aligned to a local, narrow threshold voltage adjust region, comprising the steps of: growing a first insulator layer, to be used as a gate insulator layer, on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer; depositing a second insulator layer on said polysilicon layer; forming a photoresist pattern on said second insulator layer, with a narrow opening in said photoresist pattern, exposing top surface of said polysilicon layer; forming a narrow hole opening, in said second insulator layer, by removing said second insulator layer from said narrow opening in said photoresist pattern; ion implanting a first conductivity imparting dopant, through said polysilicon layer, through said gate insulator layer, and into an area of said semiconductor substrate, defined by said narrow hole opening, to create said local, narrow threshold voltage adjust region; selectively depositing a first metal layer on the top surface of said polysilicon layer, exposed in said narrow hole opening in said second insulator layer, forming a narrow metal gate structure, overlying said polysilicon layer, in said narrow hole opening; removal of said second insulator layer, from the top surface of said polysilicon layer; patterning of said polysilicon layer, using said narrow metal gate structure as a mask, to create said narrow metal-polysilicon gate structure, comprised of overlying, said narrow metal gate structure, and underlying, narrow polysilicon gate structure, with said narrow metal-polysilicon gate structure, overlying, and self aligned to, said local, narrow threshold voltage adjust region; and forming lightly doped source and drain regions, an insulator spacer, and heavily doped source and drain regions, adjacent to said narrow metal-polysilicon gate structure.
Claim 2
Independent Claim
285 words
A method of fabricating a MOSFET device, on a semiconductor substrate, with a narrow metal-polysilicon gate structure, self aligned to a local, narrow threshold voltage adjust region, comprising the steps of: growing a first insulator layer, to be used as a gate insulator layer, on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer; depositing a second insulator layer on said polysilicon layer; forming a photoresist pattern on said second insulator layer, with a narrow opening in said photoresist pattern, exposing top surface of said polysilicon layer; forming a narrow hole opening, in said second insulator layer, by removing said second insulator layer from said narrow opening in said photoresist pattern; ion implanting a first conductivity imparting dopant, through said polysilicon layer, through said gate insulator layer, and into an area of said semiconductor substrate, defined by said narrow hole opening, to create said local, narrow threshold voltage adjust region; selectively depositing a first metal layer on the top surface of said polysilicon layer, exposed in said narrow hole opening in said second insulator layer, forming a narrow metal gate structure, overlying said polysilicon layer, in said narrow hole opening; removal of said second insulator layer, from the top surface of said polysilicon layer; patterning of said polysilicon layer, using said narrow metal gate structure as a mask, to create said narrow metal-polysilicon gate structure, comprised of overlying, said narrow metal gate structure, and underlying, narrow polysilicon gate structure, with said narrow metal-polysilicon gate structure, overlying, and self aligned to, said local, narrow threshold voltage adjust region; and forming lightly doped source and drain regions, an insulator spacer, and heavily doped source and drain regions, adjacent to said narrow metal-polysilicon gate structure.
Claim 3
Dependent Claim
43 words
The method of claim 1, wherein said first insulator layer, used as said gate insulator layer, is silicon dioxide, thermally grown in an oxygen-steam ambient, at a temperature between about 850° to 1000° C., to a thickness between about 50 to 200 Angstroms.
Claim 4
Dependent Claim
32 words
The method of claim 1, wherein said polysilicon layer is deposited using LPCVD procedures, at a temperature between about 525° to 575° C., to a thickness between about 500 to 2000 Angstroms.
Claim 5
Dependent Claim
35 words
The method of claim 1, wherein said second insulator layer is silicon oxide, deposited using LPCVD procedures, at a temperature between about 700° to 800° C., to a thickness between about 2000 to 5000 Angstroms.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein said narrow opening, in said photoresist layer, is between about 0.20 to 0.50 uM, in width.
Claim 7
Dependent Claim
35 words
The method of claim 1, wherein said narrow hole opening, in said second insulator layer, is between about 0.20 to 0.50 uM, in width, formed via anisotropic RIE procedures, using CHF 3 as an etchant.
Claim 8
Dependent Claim
62 words
The method of claim 1, wherein said first conductivity imparting dopant, used to create said local, narrow threshold adjust region, in an area of said semiconductor substrate defined by said narrow hole opening in said second insulator layer, is boron, ion implanted at an energy between about 10 to 50 KeV, at a dose between about 1E11 to 1E13 atoms/cm 2 .
Claim 9
Dependent Claim
59 words
The method of claim 1, wherein said first metal layer is tungsten, selectively deposited, on top surface of said polysilicon layer, forming said narrow metal gate structure in said narrow hole opening, via LPCVD procedures, at a temperature between about 350° to 450° C., to a thickness between about 500 to 2000 Angstroms, using tungsten hexafluoride, silane and hydrogen.
Claim 10
Dependent Claim
19 words
The method of claim 1, wherein said second insulator layer is removed using a solution of buffered hydrofluoric acid.
Claim 11
Dependent Claim
101 words
The method of claim 1, wherein said narrow polysilicon gate structure is formed via RIE patterning of said polysilicon layer, using said narrow metal gate structure as a mask, and using a fluorine based, or a chlorine based, gas as an etchant, creating said narrow metal-polysilicon gate structure, with a width between about 0.20 to 0.50 uM, self aligned to said local, narrow threshold adjust region, and comprised of an overlying, said narrow metal gate structure, at a thickness between about 500 to 2000 Angstroms, and an underlying, said polysilicon gate structure, at a thickness between about 500 to 2000 Angstroms.
Claim 12
Independent Claim
491 words
A method of fabricating a deep, submicron MOSFET device, on a semiconductor substrate, with a narrow tungsten-polysilicon gate structure, self aligned to a local, narrow threshold voltage adjust region, comprising the steps of: growing a first insulator layer, to be used as a gate insulator layer, on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer; depositing a second insulator layer on said polysilicon layer; forming a photoresist pattern on said second insulator layer, with a deep submicron opening in said photoresist pattern, exposing top surface of said polysilicon layer; forming a deep submicron hole opening, in said second insulator layer, by removing said second insulator layer, from an area defined by said deep submicron opening in said photoresist pattern; ion implanting a first conductivity imparting dopant through said polysilicon layer, through said gate insulator layer, and into an area of said semiconductor substrate, defined by said deep submicron hole opening, to create said local, narrow threshold voltage adjust region; selectively depositing a tungsten layer on the top surface of said polysilicon layer, exposed in said deep submicron hole opening, in said second insulator layer, forming a narrow tungsten gate structure, overlying said polysilicon layer, in said deep submicron hole opening; removal of said second insulator layer, from the top surface of said polysilicon layer; patterning of said polysilicon layer, not covered by said narrow tungsten gate structure, to create said narrow tungsten-polysilicon gate structure, comprised of an overlying, narrow tungsten gate structure, and an underlying, narrow polysilicon gate structure, with said narrow tungsten-polysilicon gate structure, overlying, and self aligned to, said local, narrow threshold voltage adjust region; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow tungsten-polysilicon gate structure, to form a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said narrow tungsten-polysilicon gate structure; anisotropic etching of said third insulator layer to form an insulator spacer on the sides of said narrow tungsten-polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow tungsten-polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said narrow tungsten-polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain regions, and to expose top surface of said narrow tungsten-polysilicon gate structure; depositing a metal layer on the top surface of said fourth insulator layer, on the top surface of said heavily doped source and drain region, and on top surface of said narrow tungsten-polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer to form metal contact structures to said heavily doped source and drain region, and to said narrow tungsten-polysilicon gate structure.
Claim 13
Independent Claim
491 words
A method of fabricating a deep, submicron MOSFET device, on a semiconductor substrate, with a narrow tungsten-polysilicon gate structure, self aligned to a local, narrow threshold voltage adjust region, comprising the steps of: growing a first insulator layer, to be used as a gate insulator layer, on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer; depositing a second insulator layer on said polysilicon layer; forming a photoresist pattern on said second insulator layer, with a deep submicron opening in said photoresist pattern, exposing top surface of said polysilicon layer; forming a deep submicron hole opening, in said second insulator layer, by removing said second insulator layer, from an area defined by said deep submicron opening in said photoresist pattern; ion implanting a first conductivity imparting dopant through said polysilicon layer, through said gate insulator layer, and into an area of said semiconductor substrate, defined by said deep submicron hole opening, to create said local, narrow threshold voltage adjust region; selectively depositing a tungsten layer on the top surface of said polysilicon layer, exposed in said deep submicron hole opening, in said second insulator layer, forming a narrow tungsten gate structure, overlying said polysilicon layer, in said deep submicron hole opening; removal of said second insulator layer, from the top surface of said polysilicon layer; patterning of said polysilicon layer, not covered by said narrow tungsten gate structure, to create said narrow tungsten-polysilicon gate structure, comprised of an overlying, narrow tungsten gate structure, and an underlying, narrow polysilicon gate structure, with said narrow tungsten-polysilicon gate structure, overlying, and self aligned to, said local, narrow threshold voltage adjust region; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow tungsten-polysilicon gate structure, to form a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said narrow tungsten-polysilicon gate structure; anisotropic etching of said third insulator layer to form an insulator spacer on the sides of said narrow tungsten-polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said narrow tungsten-polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said narrow tungsten-polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain regions, and to expose top surface of said narrow tungsten-polysilicon gate structure; depositing a metal layer on the top surface of said fourth insulator layer, on the top surface of said heavily doped source and drain region, and on top surface of said narrow tungsten-polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer to form metal contact structures to said heavily doped source and drain region, and to said narrow tungsten-polysilicon gate structure.
Claim 14
Dependent Claim
43 words
The method of claim 11, wherein said first insulator layer, used as said gate insulator layer, is silicon dioxide, thermally grown, in an oxygen-steam ambient, at a temperature between about 850° to 1000° C., to a thickness between about 50 to 200 Angstroms.
Claim 15
Dependent Claim
32 words
The method of claim 11, wherein said polysilicon layer is deposited using LPCVD procedures, at a temperature between about 525° to 575° C., to a thickness between about 500 to 2000 Angstroms.
Claim 16
Dependent Claim
35 words
The method of claim 11, wherein said second insulator layer is silicon oxide, deposited using LPCVD procedures, at a temperature between about 700° to 800° C., to a thickness between about 2000 to 5000 Angstroms.
Claim 17
Dependent Claim
23 words
The method of claim 11, wherein said deep submicron opening, in said photoresist layer, is between about 0.20 to 0.50 uM, in width.
Claim 18
Dependent Claim
36 words
The method of claim 11, wherein said deep submicron hole opening, in said second insulator layer, is between about 0.20 to 0.50 uM, in width, formed via anisotropic RIE procedures, using CHF 3 as an etchant.
Claim 19
Dependent Claim
59 words
The method of claim 11, wherein said first conductivity imparting dopant, used to create said local, narrow threshold voltage adjust region, in an area of said semiconductor substrate defined by said deep submicron hole opening, is boron, ion implanted at an energy between about 10 to 50 KeV, at a dose between about 1E11 to 1E13 atoms/cm 2 .
Claim 20
Dependent Claim
59 words
The method of claim 11, wherein said tungsten layer is selectively deposited, on the top surface of said polysilicon layer, forming said narrow tungsten gate structure in said deep submicron hole opening, using LPCVD procedures, at a temperature between about 350° to 450° C., to a thickness between about 500 to 2000 Angstroms, using tungsten hexafluoride, silane, and hydrogen.
Claim 21
Dependent Claim
20 words
The method of claim 11, wherein said second insulator layer is removed via use of a buffered hydrofluoric acid solution.
Claim 22
Dependent Claim
98 words
The method of claim 11, wherein said narrow polysilicon gate structure is formed via RIE patterning of said polysilicon layer, using said narrow tungsten gate structure as a mask, and using a fluorine based, or chlorine based etchant, creating said narrow tungsten-polysilicon gate structure, with a width between about 0.20 to 0.50 uM, self aligned to underlying, said local, narrow threshold voltage adjust region, and comprised of overlying, said narrow tungsten gate structure, at a thickness between about 500 to 2000 Angstroms, and underlying, said narrow polysilicon gate structure, at a thickness between about 500 to 2000 Angstroms.
References Cited (Backward Citations)
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