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US5686364A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing substrate to achieve semiconductor integrated circuits

Assignee: Shin-Etsu Handotai Co Ltd
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Filing: 1995-09-19
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Granted: 1997-11-11
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Expires: 2015-09-19
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Abstract

Abstract A method for producing for a SOI type bonded substrate for semiconductor integrated circuits which has a void areal ratio which approaches or is equal to zero %, when heat treated at temperatures on the order of 1250 DEG C. The method involves: superimposing a Si single crystal wafer having a main surface of which is covered by a Si polycrystal layer, beneath which Si single crystal islands are formed on the main surface and are isolated from each other by V grooves with interposition of a dielectric film, which V grooves are filled up by the Si polycrystal layer, and a support made from Si material between the Si polycrystal layer and a surface of the support with a dielectrically insulating layer sandwiched therebetween; and conducting heat treatment of the superimposed Si single crystal wafer and the support to effect bonding therebetween. According to the method any P-V value of recesses between the Si single crystal islands and the V grooves which are formed on the bonding surface of the Si polycrystal layer are set at 13 nm/250x250 mu m2 or less; and the heat treatment is conducted at a temperature in the range of 1100 DEG C. to 1250 DEG C.

Inventors

  • 👤 Konomu Ohki
  • 👤 Akio Kanai
  • 👤 Shinji Tanaka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 11:27
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; Y; Y10; Y10S; Y10S438/00; Y10S438/938

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 210 words
A method for producing a substrate for semiconductor integrated circuits comprising the following steps of: forming V grooves in a main surface of a first Si single crystal wafer; forming an oxide layer on the main surface of the first Si single crystal wafer and on an inner surface of each groove in the main surface; depositing a Si polycrystal layer on the main surface to fill up the grooves; smoothing a surface of the Si polycrystal layer to reduce P-V values of any recesses to be within the range of 13 nm/250×250 μm 2 or less where a P-V value is defined as the maximum depth measured in nm from the highest point of adjacent plateaus to the lowest bottom of recess within a limited area of 250×250 μm 2 around the recess; forming an oxide layer on a main surface of a second Si wafer support; superimposing the Si polycrystal layer 4 and the support with a dielectrically insulating layer lying therebetween; conducting heat treatment of the superimposed Si single crystal wafer and the support at a temperature in the range of 1100° C. to 1250° C. to effect bonding therebetween; and removing portions of another main surface region of the first silicon wafer to form isolated islands.
Claim 2
Independent Claim 210 words
A method for producing a substrate for semiconductor integrated circuits comprising the following steps of: forming V grooves in a main surface of a first Si single crystal wafer; forming an oxide layer on the main surface of the first Si single crystal wafer and on an inner surface of each groove in the main surface; depositing a Si polycrystal layer on the main surface to fill up the grooves; smoothing a surface of the Si polycrystal layer to reduce P-V values of any recesses to be within the range of 13 nm/250×250 μm 2 or less where a P-V value is defined as the maximum depth measured in nm from the highest point of adjacent plateaus to the lowest bottom of recess within a limited area of 250×250 μm 2 around the recess; forming an oxide layer on a main surface of a second Si wafer support; superimposing the Si polycrystal layer 4 and the support with a dielectrically insulating layer lying therebetween; conducting heat treatment of the superimposed Si single crystal wafer and the support at a temperature in the range of 1100° C. to 1250° C. to effect bonding therebetween; and removing portions of another main surface region of the first silicon wafer to form isolated islands.
Claim 3
Dependent Claim 38 words
A method for producing a substrate for semiconductor integrated circuits as claimed in claim 1, wherein the dielectrically insulating layer is made of silicon oxide and has a thickness in the range of 13 nm to 2000 nm.
Claim 4
Dependent Claim 32 words
A method for producing a substrate for semiconductor integrated circuits as claimed in claim 2, wherein the dielectrically insulating layer has a thickness in the range of 12 nm to 1500 nm.
Claim 5
Dependent Claim 47 words
A method for producing a substrate for semiconductor integrated circuits as claimed in claim 1 wherein the heat treatment for bonding is conducted at a temperature in the range of 1100° C. to 1250° C. and a time period in the range of 3 hours or less.

References Cited (Backward Citations)

US4851078A Cited
JPH0244749A Cited
JPH03265153A Cited
JPH0621205A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-11-10 2001-05-12 2001-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-11-10 2005-05-12 2005-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-11-10 2009-05-12 2009-11-11 $7700.00 Window Closed / Lapsed

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