US5684751A
Expired / Lapsed
US
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Dynamic memory refresh controller utilizing array voltage
Assignee: Round Rock Research LLC
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Filing: 1996-07-17
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Granted: 1997-11-04
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Expires: 2016-07-17
Abstract
Abstract Self refresh timing in a low-power dynamic memory system is governed by an oscillator having a voltage dependent resistor and a process dependent capacitor. The resistor increases in resistance to compensate for increased applied power supply voltage and variation in substrate bias voltage. The total capacitance needed for a given oscillator center frequency is made up of a plurality of capacitors having the same physical characteristics as the capacitor used in the dynamic memory cell. Power supply voltage, substrate bias voltage, and the physical characteristics of the cell capacitor affect the cell's data retention time. By compensating the oscillator for these effects, refreshing is optimally accomplished within the data retention time. A system having compensated refresh timing according to the invention is more appropriate for low power applications due to the resulting decreased power consumption.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
84 words
A method of producing a clock signal used to control the refresh cycle time of an array of a dynamic memory circuit, the frequency of the clock signal being a function of the array voltage, said method comprising the steps of: charging a capacitor with a current that is a function of the array voltage; comparing the charge on the capacitor with a threshold voltage to produce the clock signal; and discharging the capacitor at a time determined in response to the clock signal.
Claim 2
Independent Claim
84 words
A method of producing a clock signal used to control the refresh cycle time of an array of a dynamic memory circuit, the frequency of the clock signal being a function of the array voltage, said method comprising the steps of: charging a capacitor with a current that is a function of the array voltage; comparing the charge on the capacitor with a threshold voltage to produce the clock signal; and discharging the capacitor at a time determined in response to the clock signal.
Claim 3
Dependent Claim
42 words
The method of claim 1 wherein said step of charging the capacitor includes the step of applying the array voltage across a resistor having a resistance which is a function of the array voltage to produce the current for charging the capacitor.
Claim 4
Dependent Claim
30 words
The method of claim 1 additionally comprising the step of adjusting the value of the capacitor to match the value of the capacitance of the storage devices within the array.
Claim 5
Dependent Claim
23 words
The method of claim 3 wherein said step of adjusting the value includes the step of removing a capacitor by blowing a fuse.
Claim 6
Dependent Claim
30 words
The method of claim 3 herein said step of adjusting the value includes the step of determining which of a plurality of capacitors should be interconnected via a masking step.
Claim 7
Dependent Claim
35 words
The method of claim 3 wherein said step of adjusting the value includes the step of determining which of a plurality of capacitors should be interconnected via controlling the condition of at least one switch.
Claim 8
Independent Claim
94 words
A method of producing a refresh signal for controlling the refresh cycle time of the cells of an array of a dynamic memory circuit, the refresh signal having a frequency related to the array voltage, said method comprising the steps of: charging a capacitor with a current that is a function of the array voltage; comparing the charge on the capacitor to a voltage to produce a clock signal; discharging the capacitor at a time determined in response to the clock signal; and producing the refresh signal with the pulses of the clock signal.
Claim 9
Independent Claim
94 words
A method of producing a refresh signal for controlling the refresh cycle time of the cells of an array of a dynamic memory circuit, the refresh signal having a frequency related to the array voltage, said method comprising the steps of: charging a capacitor with a current that is a function of the array voltage; comparing the charge on the capacitor to a voltage to produce a clock signal; discharging the capacitor at a time determined in response to the clock signal; and producing the refresh signal with the pulses of the clock signal.
Claim 10
Dependent Claim
42 words
The method of claim 7 wherein said step of charging the capacitor includes the step of applying the array voltage across a resistor having a resistance which is a function of the array voltage to produce the current for charging the capacitor.
Claim 11
Dependent Claim
29 words
The method of claim 7 additionally comprising the step of adjusting the value of the capacitor to match the value of the capacitance of the cells of the array.
Claim 12
Dependent Claim
23 words
The method of claim 9 wherein said step of adjusting the value includes the step of removing a capacitor by blowing a fuse.
Claim 13
Dependent Claim
30 words
The method of claim 9 wherein said step of adjusting the value includes the step of determining which of a plurality of capacitors should be interconnected via a masking step.
Claim 14
Dependent Claim
35 words
The method of claim 9 wherein said step of adjusting the value includes the step of determining which of a plurality of capacitors should be interconnected via controlling the condition of at least one switch.
Claim 15
Independent Claim
90 words
A method of refreshing the cells of an array of a dynamic access memory at a frequency related to the array voltage, comprising the steps of: producing a clock signal having a frequency related to the voltage applied to the array; producing a refresh signal having a frequency related to the frequency of the clock signal; sequentially selecting the rows of the array at the frequency of the refresh signal; and reading the information out of and writing the information into each row of the array as it is selected.
Claim 16
Independent Claim
90 words
A method of refreshing the cells of an array of a dynamic access memory at a frequency related to the array voltage, comprising the steps of: producing a clock signal having a frequency related to the voltage applied to the array; producing a refresh signal having a frequency related to the frequency of the clock signal; sequentially selecting the rows of the array at the frequency of the refresh signal; and reading the information out of and writing the information into each row of the array as it is selected.
Claim 17
Dependent Claim
60 words
The method of claim 13 wherein said step of producing a clock signal includes the steps of: charging a capacitor with a current that is a function of the array voltage; comparing the charge on the capacitor with a threshold voltage to produce the clock signal; and discharging the capacitor at a time determined in response to the clock signal.
Claim 18
Dependent Claim
42 words
The method of claim 14 wherein said step of charging the capacitor includes the step of applying the array voltage across a resistor having a resistance which is a function of the array voltage to produce the current for charging the capacitor.
Claim 19
Dependent Claim
29 words
The method of claim 14 additionally comprising the step of adjusting the value of the capacitor to match the value of the capacitance of the cells of the array.
Claim 20
Dependent Claim
35 words
The method of claim 13 additionally comprising the steps of determining if a refresh period has begun and of timing out a setup period when the refresh period has begun before producing the refresh signal.
Claim 21
Dependent Claim
30 words
The method of claim 17 wherein said step of timing out a setup period includes the steps of dividing the frequency of the clock signal and counting the clock pulses.
Claim 22
Dependent Claim
21 words
The method of claim 13 wherein said step of producing a refresh signal includes the step of counting the clock pulses.
Claim 23
Dependent Claim
85 words
An oscillator for producing a clock signal used to control the refresh cycle time of an array of a dynamic memory circuit, the frequency of the clock signal being a function of the array voltage, said oscillator comprising: a capacitor; a switch for selectively charging said capacitor with a current that is a function of the array voltage; and a circuit for toggling between two output states based on the charge on said capacitor, said switch being responsive to the output state of said circuit.
Claim 24
Dependent Claim
85 words
An oscillator for producing a clock signal used to control the refresh cycle time of an array of a dynamic memory circuit, the frequency of the clock signal being a function of the array voltage, said oscillator comprising: a capacitor; a switch for selectively charging said capacitor with a current that is a function of the array voltage; and a circuit for toggling between two output states based on the charge on said capacitor, said switch being responsive to the output state of said circuit.
Claim 25
Dependent Claim
39 words
The oscillator of claim 20 additionally comprising a resistor having a resistance value that is a function of the array voltage, and wherein the array voltage is applied across said resistor to produce said current for charging said capacitor.
Claim 26
Dependent Claim
24 words
The oscillator of claim 20 wherein the value of said capacitor matches the value of the capacitance of the storage devices within the array.
Claim 27
Dependent Claim
16 words
The oscillator of claim 20 wherein said capacitor includes a plurality of capacitors interconnected by fuses.
Claim 28
Dependent Claim
17 words
The oscillator of claim 20 wherein said capacitor includes a plurality of capacitors interconnected by a conductor.
Claim 29
Dependent Claim
16 words
The oscillator of claim 20 wherein said capacitor includes a plurality of capacitors interconnect by switches.
Claim 30
Dependent Claim
103 words
A refresh control circuit for producing a refresh signal for controlling the refresh cycle time of the cells of an array of a dynamic memory circuit, the refresh signal having a frequency related to the array voltage, said refresh control circuit comprising: a capacitor; a switch for selectively charging said capacitor with a current that is a function of the array voltage; a circuit for toggling between two output states based on the charge on said capacitor, said switch being responsive to the output state of said circuit; and a logic circuit for producing the refresh signal in response to the clock signal.
Claim 31
Dependent Claim
103 words
A refresh control circuit for producing a refresh signal for controlling the refresh cycle time of the cells of an array of a dynamic memory circuit, the refresh signal having a frequency related to the array voltage, said refresh control circuit comprising: a capacitor; a switch for selectively charging said capacitor with a current that is a function of the array voltage; a circuit for toggling between two output states based on the charge on said capacitor, said switch being responsive to the output state of said circuit; and a logic circuit for producing the refresh signal in response to the clock signal.
Claim 32
Dependent Claim
132 words
A dynamic random access memory having a self refreshing rate that is related to the array voltage, comprising: an array made up of rows and columns of memory cells; a first circuit for determining if a refresh period has begun; an oscillator, responsive to said first circuit, for producing a clock signal having a frequency related to the voltage applied to said array; a second circuit for timing out a setup time period in response to said oscillator; a third circuit for producing a refresh signal in response to said oscillator; a fourth circuit for sequentially selecting said rows of said array at the frequency of said refresh signal; and a fifth circuit for reading information out of and writing the information into each row of said array as it is selected.
Claim 33
Dependent Claim
132 words
A dynamic random access memory having a self refreshing rate that is related to the array voltage, comprising: an array made up of rows and columns of memory cells; a first circuit for determining if a refresh period has begun; an oscillator, responsive to said first circuit, for producing a clock signal having a frequency related to the voltage applied to said array; a second circuit for timing out a setup time period in response to said oscillator; a third circuit for producing a refresh signal in response to said oscillator; a fourth circuit for sequentially selecting said rows of said array at the frequency of said refresh signal; and a fifth circuit for reading information out of and writing the information into each row of said array as it is selected.
Claim 34
Dependent Claim
59 words
The dynamic random access memory of claim 27 wherein said oscillator includes: a capacitor; a switch for selectively charging said capacitor with a current that is a function of said array voltage; and a circuit for toggling between two output states based on the charge on said capacitor, said switch being responsive to the output state of said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |