Patent US5684727A successfully refreshed from Google Patents.
US5684727A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed correlator
Assignee: Neptune Operations Ltd
•
Filing: 1996-02-07
•
Granted: 1997-11-04
•
Expires: 2016-02-07
Abstract
Abstract A high-speed correlator includes a serial-to-parallel convertor, and a pattern detector. The serial-to-parallel converter converts from ECL to TTL logic. The pattern detector includes a fast latch data pipe, high-speed RAMs and a fast adder. The data pipe applies the received data to the high-speed RAMs as address bits. Depending upon position and errors in the synchronization pattern various locations in the RAM are addressed. By preloading the RAM with appropriate data for a given synchronization pattern, position and error information is read from the addressed location and applied to correlate the data and determine the error content.
Inventors
- 👤 William Norman Campbell
- 👤 Kjell Lee Magnussen
- 👤 William John Kury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:38
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; G; G06; G06F; G06F17/00; G06F17/10; G06F17/15
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
146 words
A high speed correlator comprising: a serial-to-parallel converter; data and clock inputs connected to the serial-to-parallel converter; a plurality of parallel data latches sequentially connected to the serial-to-parallel converter; a plurality of high-speed RAM, each having an address bus and a data bus, the address bus of each RAM connected to predetermined outputs of the parallel data latches for applying sequential bits of data signal as a first part of respective addresses; one RAM having a predetermined number of data bus lines connected to the address busses of the remaining RAM for applying data bits as a second part of respective addresses of the remaining RAM; an adder coupled to a second predetermined number of data bus lines of the high-speed RAM; and a comparator connected to the adder and a predetermined error tolerance indication and having an output for indicating correlation of the data signal.
Claim 2
Dependent Claim
146 words
A high speed correlator comprising: a serial-to-parallel converter; data and clock inputs connected to the serial-to-parallel converter; a plurality of parallel data latches sequentially connected to the serial-to-parallel converter; a plurality of high-speed RAM, each having an address bus and a data bus, the address bus of each RAM connected to predetermined outputs of the parallel data latches for applying sequential bits of data signal as a first part of respective addresses; one RAM having a predetermined number of data bus lines connected to the address busses of the remaining RAM for applying data bits as a second part of respective addresses of the remaining RAM; an adder coupled to a second predetermined number of data bus lines of the high-speed RAM; and a comparator connected to the adder and a predetermined error tolerance indication and having an output for indicating correlation of the data signal.
Claim 3
Dependent Claim
23 words
A high-speed correlator as claimed in claim 1 further comprising a plurality of latches connected to the data busses of the high-speed RAMs.
Claim 4
Dependent Claim
15 words
A high-speed correlator as claimed in claim 1 wherein the serial-to-parallel converter includes a shift-register.
Claim 5
Dependent Claim
21 words
A high-speed correlator as claimed in claim 3 wherein the serial-to-parallel converter includes a clock divider having a divided clock output.
Claim 6
Dependent Claim
21 words
A high-speed correlator or as claimed in claim 4 wherein the serial-to-parallel converter includes ECL-to-TTL (Emitter-Coupled Logic to Transistor-Transistor Logic) converters.
Claim 7
Dependent Claim
22 words
A high-speed correlator as claimed in claim 5 wherein the ECL-to-TTL converters include a data latch connected to the divided clock output.
Claim 8
Dependent Claim
23 words
A high-speed correlator as claimed in claim 5 wherein the ECL-to-TTL convertors include a ECL-to-TTL clock converter connected to the divided clock output.
Claim 9
Dependent Claim
35 words
A high-speed correlator as claimed in claim 1 wherein the plurality of latches comprises six parallel latches connected sequentially, a first latch connected to the serial-to-parallel converter each subsequent latch connected to the previous latch.
Claim 10
Dependent Claim
28 words
A high-speed correlator as claimed in claim 8 where the plurality of high-speed RAM comprises first, second, and third RAM and said one RAM is the second RAM.
Claim 11
Dependent Claim
27 words
A high-speed correlator as claimed in claim 9 wherein the address bus of the first RAM is connected to predetermined outputs of the first and second latch.
Claim 12
Dependent Claim
28 words
A high-speed correlator as claimed in claim 10 wherein the address bus of the second RAM is connected to predetermined outputs of the first, second, and third latches.
Claim 13
Dependent Claim
28 words
A high-speed correlator as claimed in claim 11 wherein the address bus of the third RAM is connected to predetermined outputs of the fourth, fifth and sixth latches.
References Cited (Backward Citations)
US4112498A
Cited
US4701939A
Cited
US4835768A
Cited
US5140617A
Cited
US5140618A
Cited
US5172334A
Cited
US5251239A
Cited
US5218562A
Cited
US5241568A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |