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US5682528A
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Spoon-feed initialization in a multiprocessor system
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1995-12-22
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Granted: 1997-10-28
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Expires: 2015-12-22
Abstract
Abstract The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a sequence of software code, and then a first instruction loop is implemented with that software code. The processor is then released from a reset state, and the first instruction loop is executed. This first instruction loop is capable of being executed for an indefinite length of time, and it can execute software instructions on a periodic basis. The first instruction loop is then modified into a second instruction loop. The first and second instruction loops have at least one different instruction. The processor within the system of multiple processors is thus initialized.
Inventors
- 👤 William E. Baker
- 👤 David P. Sonnier
- 👤 Daniel L. Fowler
- 👤 Frank A. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:48
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/177; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4405
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A method for initial execution of a software program by a processor in a multiprocessor system, said multiprocessor system including registers, said method comprising the steps of: loading said registers with a sequence of software code; implementing a first instruction loop with said sequence of software code, said first instruction loop capable of being executed for an indefinite length of time, said first instruction loop capable of executing at least one software instruction on a periodic basis; releasing said processor from a reset state; executing said first instruction loop; and modifying said first instruction loop to a second instruction loop, said second instruction loop having at least one different instruction from said first instruction loop; whereby said processor in said system of multiple processors is initialized.
Claim 2
Independent Claim
126 words
A method for initial execution of a software program by a processor in a multiprocessor system, said multiprocessor system including registers, said method comprising the steps of: loading said registers with a sequence of software code; implementing a first instruction loop with said sequence of software code, said first instruction loop capable of being executed for an indefinite length of time, said first instruction loop capable of executing at least one software instruction on a periodic basis; releasing said processor from a reset state; executing said first instruction loop; and modifying said first instruction loop to a second instruction loop, said second instruction loop having at least one different instruction from said first instruction loop; whereby said processor in said system of multiple processors is initialized.
Claim 3
Dependent Claim
42 words
The method for initial execution of a software program by a processor in a multiprocessor system of claim 1, wherein said first instruction loop is contained in said registers, and said registers are implemented at a reset vector location of said processor.
Claim 4
Dependent Claim
43 words
The method for initial execution of a software program by a processor in a multiprocessor system of claim 1, wherein said processor executes said first instruction loop multiple times before an external processor modifies said first instruction loop into said second instruction loop.
Claim 5
Dependent Claim
39 words
The method for initial execution of a software program by a processor in a multiprocessor system of claim 1, wherein instructions contained in said first instruction loop are limited to instructions producing a same result regardless of execution times.
Claim 6
Dependent Claim
46 words
The method for initial execution of a software program by a processor in a multiprocessor system of claim 1, further comprising the step of placing a branch instruction in said second instruction loop to transfer control from said second instruction loop to a loaded code image.
Claim 7
Dependent Claim
96 words
A multiprocessing system comprising: a register; a sequence of software code for implementing a first instruction loop in said register, said first instruction loop capable of being executed for an indefinite length of time, and said first instruction loop capable of executing at least one software instruction on a periodic basis; a first processor for executing said first instruction loop; and a second processor for modifying said first instruction loop to a second instruction loop, said second instruction loop having at least one different instruction from said first instruction loop; whereby said first processor is initialized.
Claim 8
Dependent Claim
96 words
A multiprocessing system comprising: a register; a sequence of software code for implementing a first instruction loop in said register, said first instruction loop capable of being executed for an indefinite length of time, and said first instruction loop capable of executing at least one software instruction on a periodic basis; a first processor for executing said first instruction loop; and a second processor for modifying said first instruction loop to a second instruction loop, said second instruction loop having at least one different instruction from said first instruction loop; whereby said first processor is initialized.
Claim 9
Dependent Claim
26 words
The multiprocessing system of claim 6, wherein instructions contained in said first instruction loop are limited to instructions producing a same result regardless of execution times.
Claim 10
Dependent Claim
30 words
The multiprocessing system of claim 6, wherein said first instruction loop is contained in said register, and said register is implemented at a reset vector location of said first processor.
Claim 11
Dependent Claim
31 words
The multiprocessing system of claim 6, wherein said first processor executes said first instruction loop multiple times before said second processor modifies said first instruction loop into said second instruction loop.
Claim 12
Dependent Claim
31 words
The multiprocessing system of claim 8, wherein said second processor modifies said first instruction loop into said second instruction loop by changing at least one opcode in said reset vector location.
Claim 13
Dependent Claim
29 words
The multiprocessing system of claim 6, wherein said second processor modifies said first instruction loop into said second instruction loop by changing one instruction in said first instruction loop.
Claim 14
Dependent Claim
15 words
The multiprocessing system of claim 6, wherein said register is located in a memory controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-27 | 2001-04-28 | 2001-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-27 | 2005-04-28 | 2005-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-27 | 2009-04-28 | 2009-10-28 | $7700.00 | Window Closed / Lapsed |