Horizontally scaling image signals according to a selected scaling mode

Claim 1

A computer-implemented method for horizontally scaling image signals, comprising the steps of: (a) receiving a plurality of image signals corresponding to an image; (b) generating one or more first-sum signals using a processor by adding together one or more pairs of image signals; (c) generating one or more second-sum signals using the processor by adding together one or more pairs of the first-sum signals; (d) generating one or more first-average signals using the processor in accordance with the first-sum signals; (e) generating one or more second-average signals using the processor in accordance with the second-sum signals; and (f) selectively storing the image signals, the first-average signals, and the second-average signals into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation, wherein: step (a) comprises the step of receiving a first set of image signals mem0, mem1, mem2, and mem3 corresponding to a row of the image; step (b) comprises the steps of; (1) generating a first-sum signal sum2lo by adding the image signals mem0 and meta1; and (2) generating a first-sum signal sum2hi by adding the image signals mem2 and mem3; step (c) comprises the step of generating a second-sum signal sum4 by adding the first-sum signals sum2lo and sum2hi; step (d) comprises the steps of: (1) generating a first-average signal ave2lo by shifting the first-sum signal sum2lo right one bit; and (2) generating a first-average signal ave2hi by shifting the first-sum signal sum2hi right one bit; step (e) comprises the step of generating a second-average signal ave4 by shifting the first-average signal sum4 right two bits; step (f) comprises the steps of; (1) storing the image signal mem0 in a first register, the image signal mem1 in a second register, the image signal mem2 in a third register, and the image signal mem3 in a fourth register, in accordance with the selection of 1:1 scaling; (2) storing the first-average signal ave2lo in the first register and the first-average signal ave2hi in the second register, repeating steps (a)-(e) for a second set of image signals mem0, mem1, mem2, and mem3 of the image, and storing the first-average signal ave2lo in the third register and the first-average signal ave2hi in the fourth register, in accordance with the selection of 2:1 scaling; and (3) storing the second-average signal ave4 in the first register, repeating steps (a)-(e) for a second set of image signals mem0, mem1, mem2, and mem3 of the image, storing the second-average signal ave4 in the second register, repeating steps (a)-(e) for a third set of image signals mem0, mem1, mem2, and mem3 of the image, storing the second-average signal ave4 in the third register, repeating steps (a)-(e) for a fourth set of image signals mem0, mem1, mem2, and mem3 of the image, and storing the second-average signal ave4 in the fourth register, in accordance with the selection of 4:1 scaling.

Claim 5

An apparatus for horizontally scaling image signals, comprising: (a) means for generating one or more first-sum signals by adding together one or more pairs of image signals corresponding to an image; (b) means for generating one or more second-sum signals by adding together one or more pairs of the first-sum signals; (c) means for generating one or more first-average signals in accordance with the first-sum signals; (d) means for generating one or more second-average signals in accordance with the second-sum signals; and (e) means for selectively storing the image signals, the first-average signals, and the second-average signals into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation, wherein: means (a) comprises: (1) means for generating a first-sum signal sum2lo by adding image signals mem0 and mem1 of a first set of image signals mem0, mem1, mem2, and mem3 corresponding to a row of the image; and (2) means for generating a first-sum signal sum2hi by adding the image signals mem2 and mem3; means (b) generates a second-sum signal sum4 by adding the first-sum signals sum2lo and sum2hi; means (c) comprises: (1) means for generating a first-average signal ave2lo by shifting the first-sum signal sum2lo right one bit; and (2) means for generating a first-average signal ave2hi by shifting the first-sum signal sum2hi right one bit; means (d) generates a second-average signal ave4 by shifting the first-average signal sum4 right two bits; means (e) comprises: (1) means for storing the image signal mem0 in a first register, the image signal me1 in a second register, the image signal mem2 in a third register, and the image signal mem3 in a fourth register, in accordance with the selection of 1:1 scaling; (2) means for storing the first-average signal ave2lo in the first register and the first-average signal ave2hi in the second register, wherein the processing of means (a)-(d) is repeated for a second set of image signals mem0, mem1, mem2, and mem3 of the image, and means (e)(2) stores the first-average signal ave2lo in the third register and the first-average signal ave2hi in the fourth register, in accordance with the selection of 2:1 scaling; and (3) means for storing the second-average signal ave4 in the first register, wherein the processing of means (a)-(e) is repeated for a second set of image signals mem0, mem1, mem2, and mem3 of the image, means (e)(3) stores the second-average signal ave4 in the second register, the processing of means (a)-(d) is repeated for a third set of image signals mem0, mem1, mem2, and mem3 of the image, means (e)(3) stores the second-average signal ave4 in the third register, the processing of means (a)-(d) is repeated for a fourth set of image signals mem0, mem1, mem2, and mem3 of the image, and means (e)(3) stores the second-average signal ave4 in the fourth register, in accordance with the selection of 4:1 scaling.

Claim 6

An apparatus for horizontally scaling image signals, comprising: (a) means for generating one or more first-sum signals by adding together one or more pairs of image signals corresponding to an image; (b) means for generating one or more second-sum signals by adding together one or more pairs of the first-sum signals; (c) means for generating one or more first-average signals in accordance with the first-sum signals; (d) means for generating one or more second-average signals in accordance with the second-sum signals; and (e) means for selectively storing the image signals, the first-average signals, and the second-average signals into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation, wherein: means (a) comprises: (1) means for generating a first-sum signal sum2lo by adding image signals mem0 and mem1 of a first set of image signals mem0, mem1, mem2, and mem3 corresponding to a row of the image; and (2) means for generating a first-sum signal sum2hi by adding the image signals mem2 and mem3; means (b) generates a second-sum signal sum4 by adding the first-sum signals sum2lo and sum2hi; means (c) comprises: (1) means for generating a first-average signal ave2lo by shifting the first-sum signal sum2lo right one bit; and (2) means for generating a first-average signal ave2hi by shifting the first-sum signal sum2hi right one bit; means (d) generates a second-average signal ave4 by shifting the first-average signal sum4 right two bits; means (e) comprises: (1) means for storing the image signal mem0 in a first register, the image signal me1 in a second register, the image signal mem2 in a third register, and the image signal mem3 in a fourth register, in accordance with the selection of 1:1 scaling; (2) means for storing the first-average signal ave2lo in the first register and the first-average signal ave2hi in the second register, wherein the processing of means (a)-(d) is repeated for a second set of image signals mem0, mem1, mem2, and mem3 of the image, and means (e)(2) stores the first-average signal ave2lo in the third register and the first-average signal ave2hi in the fourth register, in accordance with the selection of 2:1 scaling; and (3) means for storing the second-average signal ave4 in the first register, wherein the processing of means (a)-(e) is repeated for a second set of image signals mem0, mem1, mem2, and mem3 of the image, means (e)(3) stores the second-average signal ave4 in the second register, the processing of means (a)-(d) is repeated for a third set of image signals mem0, mem1, mem2, and mem3 of the image, means (e)(3) stores the second-average signal ave4 in the third register, the processing of means (a)-(d) is repeated for a fourth set of image signals mem0, mem1, mem2, and mem3 of the image, and means (e)(3) stores the second-average signal ave4 in the fourth register, in accordance with the selection of 4:1 scaling.

Claim 19

A system for processing image signals, comprising: (a) a host processor; and (b) an image processing subsystem, electrically connected to the host processor, wherein the image processing subsystem comprises: (1) an external memory device; and (2) a horizontal scaler, electrically connected to the external memory device, wherein the horizontal scaler comprises: (i) one or more first-sum adders for generating one or more first-sum signals by adding together one or more pairs of image signals corresponding to an image; (ii) one or more second-sum adders for generating one or more second-sum signals by adding together one or more pairs of the first-sum signals; (iii) one or more first-average shifters for generating one or more first-average signals in accordance with the first-sum signals; (iv) one or more second-average shifters for generating one or more second-average signals in accordance with the second-sum signals; and (v) means for selectively storing the image signals, the first-average signals, and the second-average signals into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation, wherein: the one or more first-sum adders comprises: (a) a first adder for generating first-sum signals sum2lo by adding image signals mem0 and mem1 of the image; and (b) a second adder for generating a first-sum signals sum2hi by adding image signals mem2 and mem3 of the image; the one or more second-sum adders comprises a third adder for generating second-sum signals sum4 by adding the first-sum signals sum2lo and sum2hi; the one or more first-average shifters comprises: (a) first shifter for generating first-average signals ave2lo by shifting the first-sum signals sum2lo right one bit; and (b) a second shifter for generating first-average signals ave2hi by shifting the first-sum signals sum2hi right one bit; the one or more second-average shifters comprises a third shifter for generating second-average signals ave4 by shifting the first-average signals sum4 right two bits; means (v) comprises: (a) a first multiplexer; (b) a second multiplexer; (c) a third multiplexer; (d) a fourth multiplexer; (e) a first register; (f) a second register; (g) a third register; and (h) a fourth register, wherein: the first multiplexer receives the image signals mem3, a first subset of the first-average signals ave2hi, and a first subset of the second-average signals ave4; the second multiplexer receives the image signals mem2, a first subset of the first-average signals ave2lo, and a second subset of the second-average signals ave4; the third multiplexer receives the image signals mem1, a second subset of the first-average signals ave2hi, and a third subset of the second-average signals ave4; the fourth multiplexer receives the image signals mem0, a second subset of the first-average signals ave2lo, and a fourth subset of the second-average signals ave4; when 1:1 scaling is selected: the first multiplexer transmits the image signals mem3 to the first register; the second multiplexer transmits the image signals mem2 to the second register; the third multiplexer transmits the image signals mem1 to the third register; the fourth multiplexer transmits the image signals mem0 to the fourth register; when 2:1 scaling is selected: the first multiplexer transmits the first subset of the first-average signals ave2hi to the first register; the second multiplexer transmits the first subset of the first-average signals ave2lo to the second register; the third multiplexer transmits the second subset of the first-average signals ave2hi to the third register; the fourth multiplexer transmits the second subset of the first-average signals ave2lo to the fourth register; when 4:1 scaling is selected: the first multiplexer transmits the first subset of the second-average signals ave4 to the first register; the second multiplexer transmits the second subset of the second-average signals ave4 to the second register; the third multiplexer transmits the third subset of the second-average signals ave4 to the third register; and the fourth multiplexer transmits the fourth subset of the second-average signals ave4 to the fourth register.

Claim 20

A system for processing image signals, comprising: (a) a host processor; and (b) an image processing subsystem, electrically connected to the host processor, wherein the image processing subsystem comprises: (1) an external memory device; and (2) a horizontal scaler, electrically connected to the external memory device, wherein the horizontal scaler comprises: (i) one or more first-sum adders for generating one or more first-sum signals by adding together one or more pairs of image signals corresponding to an image; (ii) one or more second-sum adders for generating one or more second-sum signals by adding together one or more pairs of the first-sum signals; (iii) one or more first-average shifters for generating one or more first-average signals in accordance with the first-sum signals; (iv) one or more second-average shifters for generating one or more second-average signals in accordance with the second-sum signals; and (v) means for selectively storing the image signals, the first-average signals, and the second-average signals into a plurality of registers in accordance with the selection of a mode of operation of a plurality of modes of operation, wherein: the one or more first-sum adders comprises: (a) a first adder for generating first-sum signals sum2lo by adding image signals mem0 and mem1 of the image; and (b) a second adder for generating a first-sum signals sum2hi by adding image signals mem2 and mem3 of the image; the one or more second-sum adders comprises a third adder for generating second-sum signals sum4 by adding the first-sum signals sum2lo and sum2hi; the one or more first-average shifters comprises: (a) first shifter for generating first-average signals ave2lo by shifting the first-sum signals sum2lo right one bit; and (b) a second shifter for generating first-average signals ave2hi by shifting the first-sum signals sum2hi right one bit; the one or more second-average shifters comprises a third shifter for generating second-average signals ave4 by shifting the first-average signals sum4 right two bits; means (v) comprises: (a) a first multiplexer; (b) a second multiplexer; (c) a third multiplexer; (d) a fourth multiplexer; (e) a first register; (f) a second register; (g) a third register; and (h) a fourth register, wherein: the first multiplexer receives the image signals mem3, a first subset of the first-average signals ave2hi, and a first subset of the second-average signals ave4; the second multiplexer receives the image signals mem2, a first subset of the first-average signals ave2lo, and a second subset of the second-average signals ave4; the third multiplexer receives the image signals mem1, a second subset of the first-average signals ave2hi, and a third subset of the second-average signals ave4; the fourth multiplexer receives the image signals mem0, a second subset of the first-average signals ave2lo, and a fourth subset of the second-average signals ave4; when 1:1 scaling is selected: the first multiplexer transmits the image signals mem3 to the first register; the second multiplexer transmits the image signals mem2 to the second register; the third multiplexer transmits the image signals mem1 to the third register; the fourth multiplexer transmits the image signals mem0 to the fourth register; when 2:1 scaling is selected: the first multiplexer transmits the first subset of the first-average signals ave2hi to the first register; the second multiplexer transmits the first subset of the first-average signals ave2lo to the second register; the third multiplexer transmits the second subset of the first-average signals ave2hi to the third register; the fourth multiplexer transmits the second subset of the first-average signals ave2lo to the fourth register; when 4:1 scaling is selected: the first multiplexer transmits the first subset of the second-average signals ave4 to the first register; the second multiplexer transmits the second subset of the second-average signals ave4 to the second register; the third multiplexer transmits the third subset of the second-average signals ave4 to the third register; and the fourth multiplexer transmits the fourth subset of the second-average signals ave4 to the fourth register.