Transform processor system having reduced processing bandwith

Claim 2

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a coefficient processor generating transform coefficients in response to the driving function signal; a first transform processor coupled to the coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the transform coefficients; a second transform processor coupled to the coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same transform coefficients as used for the generation of the first transform point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 3

A transform processor system as set forth in claim 1, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 4

A transform processor system as set forth in claim 1, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the coefficient processor is an incremental coefficient processor generating the plurality of transform coefficients by incrementally processing the incremental driving function signal.

Claim 5

A transform processor system as set forth in claim 1, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the coefficient processor is an incremental coefficient processor generating the plurality of transform coefficients by incrementally processing the incremental driving function signal, wherein the first transform processor is a first incremental transform processor generating the first transformed point by incrementally processing the first one of the plurality of input points stored by the memory in response to the transform coefficients, and wherein the second transform processor is a second incremental transform processor generating the second transformed point by incrementally processing the second one of the plurality of input points stored by the memory in response to the same transform coefficients.

Claim 6

A transform processor system as set forth in claim 1, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 7

A transform processor system as set forth in claim 1, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the coefficient processor generates the transform coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 8

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a coefficient processor generating a plurality of coefficients in response to the driving function signal; a transform processor coupled to the coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 9

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a coefficient processor generating a plurality of coefficients in response to the driving function signal; a transform processor coupled to the coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 10

A transform processor system as set forth in claim 7, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 11

A transform processor system as set forth in claim 7, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the coefficient processor is an incremental coefficient processor generating the plurality of coefficients by incrementally processing the incremental driving function signal.

Claim 12

A transform processor system as set forth in claim 7, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the coefficient processor is an incremental coefficient processor generating the plurality of coefficients by incrementally processing the incremental driving function signal, and wherein the transform processor is an incremental transform processor generating the plurality of transformed points by incrementally processing the plurality of input points stored by the memory in response to the same coefficients.

Claim 13

A transform processor system as set forth in claim 7, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 14

A transform processor system as set forth in claim 7, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the coefficient processor generates the plurality of coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 15

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a hierarchal coefficient processor generating hierarchal transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the hierarchal coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the hierarchal transform coefficients; a second transform processor coupled to the hierarchal coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same hierarchal transform coefficients as used for the generation of the first transform point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 16

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a hierarchal coefficient processor generating hierarchal transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the hierarchal coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the hierarchal transform coefficients; a second transform processor coupled to the hierarchal coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same hierarchal transform coefficients as used for the generation of the first transform point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 17

A transform processor system as set forth in claim 13, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 18

A transform processor system as set forth in claim 13, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the hierarchal coefficient processor is an incremental hierarchal coefficient processor generating the hierarchal transform coefficients by incrementally processing the incremental driving function signal.

Claim 19

A transform processor system as set forth in claim 13, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the hierarchal coefficient processor is an incremental hierarchal coefficient processor generating the hierarchal transform coefficients by incrementally processing the incremental driving function signal, wherein the first transform processor is a first incremental transform processor generating the first transformed point by incrementally processing the first one of the plurality of input points stored by the memory in response to the hierarchal transform coefficients, and wherein the second transform processor is a second incremental transform processor generating the second transformed point by incrementally processing the second one of the plurality of input points stored by the memory in response to the same hierarchal transform coefficients.

Claim 20

A transform processor system as set forth in claim 13, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 21

A transform processor system as set forth in claim 13, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the hierarchal coefficient processor generates the hierarchal transform coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 22

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a hierarchal coefficient processor generating a plurality of hierarchal coefficients in response to the driving function signal; a transform processor coupled to the hierarchal coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same hierarchal coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 23

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a hierarchal coefficient processor generating a plurality of hierarchal coefficients in response to the driving function signal; a transform processor coupled to the hierarchal coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same hierarchal coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 24

A transform processor system as set forth in claim 19, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 25

A transform processor system as set forth in claim 19, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the hierarchal coefficient processor is an incremental hierarchal coefficient processor generating the plurality of hierarchal coefficients by incrementally processing the incremental driving function signal.

Claim 26

A transform processor system as set forth in claim 19, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the hierarchal coefficient processor is an incremental hierarchal coefficient processor generating the plurality of hierarchal coefficients by incrementally processing the incremental driving function signal, and wherein the transform processor is an incremental transform processor generating the plurality of transformed points by incrementally processing the plurality of input points stored by the memory in response to the same hierarchal coefficients.

Claim 27

A transform processor system as set forth in claim 19, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 28

A transform processor system as set forth in claim 19, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the hierarchal coefficient processor generates the plurality of hierarchal coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 29

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating a first driving function signal related to a first one of the input points stored by the memory and a second driving function signal related to a second one of the input points stored by the memory; a first detector coupled to the input circuit and generating a first detector signal indicative of a change in the first driving function signal; a second detector coupled to the input circuit and generating a second detector signal indicative of a change in the second driving function signal; a first transform processor coupled to the first detector and to the memory and transforming the first one of the input points stored by the memory in response to the first detector signal; a second transform processor coupled to the second detector and to the memory and transforming the second one of the input points stored by the memory in response to the second detector signal; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 30

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating a first driving function signal related to a first one of the input points stored by the memory and a second driving function signal related to a second one of the input points stored by the memory; a first detector coupled to the input circuit and generating a first detector signal indicative of a change in the first driving function signal; a second detector coupled to the input circuit and generating a second detector signal indicative of a change in the second driving function signal; a first transform processor coupled to the first detector and to the memory and transforming the first one of the input points stored by the memory in response to the first detector signal; a second transform processor coupled to the second detector and to the memory and transforming the second one of the input points stored by the memory in response to the second detector signal; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 31

A transform processor system as set forth in claim 25, wherein the input circuit is an incremental input circuit generating the first driving function signal as a first incremental driving function signal and the second driving function signal as a second incremental driving function signal.

Claim 32

A transform processor system as set forth in claim 25, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 33

A transform processor system as set forth in claim 25, wherein the input circuit includes a rotation device generating the first driving function signal as a rotational driving function signal related to the first one of the input points stored by the memory.

Claim 34

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating driving function signals related to the input points stored by the memory; a plurality of detectors coupled to the input circuit and generating detector signals indicative of changes in the driving function signals; a transform processor coupled to the plurality of detectors and to the memory and transforming the input points stored by the memory in response to the detector signals; and an output circuit coupled to the transform processor and generating transformed output signals in response to the transformed points.

Claim 35

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating driving function signals related to the input points stored by the memory; a plurality of detectors coupled to the input circuit and generating detector signals indicative of changes in the driving function signals; a transform processor coupled to the plurality of detectors and to the memory and transforming the input points stored by the memory in response to the detector signals; and an output circuit coupled to the transform processor and generating transformed output signals in response to the transformed points.

Claim 36

A transform processor system as set forth in claim 29, wherein the input circuit is an incremental input circuit generating the driving function signals as incremental driving function signals.

Claim 37

A transform processor system as set forth in claim 29, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 38

A transform processor system as set forth in claim 29, wherein the input circuit includes a rotation device generating at least one of the driving function signals as a rotational driving function signal.

Claim 39

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating a first driving function signal related to a first one of the input points stored by the memory and a second driving function signal related to a second one of the input points stored by the memory; a first detector coupled to the input circuit and generating a first detector signal indicative of a change in the first driving function signal; a second detector coupled to the input circuit and generating a second detector signal indicative of a change in the second driving function signal; a first transform processor coupled to the first detector and to the memory and transforming the first one of the input points stored by the memory when the first detector signal is indicative of a change in the first driving function signal and bypassing transforming of the first one of the input points when the first detector signal is indicative of no change in the first driving function signal; a second transform processor coupled to the second detector and to the memory and transforming the second one of the input points stored by the memory when the second detector signal is indicative of a change in the second driving function signal and bypassing transforming of the second one of the input points when the second detector signal is indicative of no change in the second driving function signal; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 40

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating a first driving function signal related to a first one of the input points stored by the memory and a second driving function signal related to a second one of the input points stored by the memory; a first detector coupled to the input circuit and generating a first detector signal indicative of a change in the first driving function signal; a second detector coupled to the input circuit and generating a second detector signal indicative of a change in the second driving function signal; a first transform processor coupled to the first detector and to the memory and transforming the first one of the input points stored by the memory when the first detector signal is indicative of a change in the first driving function signal and bypassing transforming of the first one of the input points when the first detector signal is indicative of no change in the first driving function signal; a second transform processor coupled to the second detector and to the memory and transforming the second one of the input points stored by the memory when the second detector signal is indicative of a change in the second driving function signal and bypassing transforming of the second one of the input points when the second detector signal is indicative of no change in the second driving function signal; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 41

A transform processor system as set forth in claim 33, wherein the input circuit is an incremental input circuit generating the first driving function signal as a first incremental driving function signal and the second driving function signal as a second incremental driving function signal.

Claim 42

A transform processor system as set forth in claim 33, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 43

A transform processor system as set forth in claim 33, wherein the input circuit includes a rotation device generating the first driving function signal as a rotational driving function signal related to the first one of the input points stored by the memory.

Claim 44

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating driving function signals related to the input points stored by the memory; a plurality of detectors coupled to the input circuit and generating detector signals indicative of changes in the driving function signals; a transform processor coupled to the plurality of detectors and to the memory and transforming the input points stored by the memory when the detector signals are indicative of changes in the driving function signals and bypassing transforming of the input points when the detector signals are indicative of no change in the driving function signals; and an output circuit coupled to the transform processor and generating transformed output signals in response to the transformed points.

Claim 45

A transform processor system comprising: a memory storing a plurality of input points, each input point having a plurality of parameters; an input circuit generating driving function signals related to the input points stored by the memory; a plurality of detectors coupled to the input circuit and generating detector signals indicative of changes in the driving function signals; a transform processor coupled to the plurality of detectors and to the memory and transforming the input points stored by the memory when the detector signals are indicative of changes in the driving function signals and bypassing transforming of the input points when the detector signals are indicative of no change in the driving function signals; and an output circuit coupled to the transform processor and generating transformed output signals in response to the transformed points.

Claim 46

A transform processor system as set forth in claim 37, wherein the input circuit is an incremental input circuit generating the driving function signals as incremental driving function signals.

Claim 47

A transform processor system as set forth in claim 37, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 48

A transform processor system as set forth in claim 37, wherein the input circuit includes a rotation device generating at least one of the driving function signals as a rotational driving function signal.

Claim 49

A transform processor system comprising: a translation input circuit generating a translation driving function signal; a rotation input circuit generating a rotation driving function signal; and a transform processor coupled to the translation input device and to the rotation input device and generating transformed output signals in response to the translation driving function signal and in response to the rotation driving function signal, wherein the transform processor includes a) a memory storing a plurality of points each point having at least two coordinates, b) a coefficient processor generating a plurality of coefficients in response to the translation driving function signal and in response to the rotation driving function signal, c) a transform circuit coupled to the coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of points stored by the memory and in response to the same coefficients, and d) an output circuit coupled to the transform circuit and generating the transformed output signals in response to the plurality of transformed points.

Claim 50

A transform processor system comprising: a translation input circuit generating a translation driving function signal; a rotation input circuit generating a rotation driving function signal; and a transform processor coupled to the translation input device and to the rotation input device and generating transformed output signals in response to the translation driving function signal and in response to the rotation driving function signal, wherein the transform processor includes a) a memory storing a plurality of points each point having at least two coordinates, b) a coefficient processor generating a plurality of coefficients in response to the translation driving function signal and in response to the rotation driving function signal, c) a transform circuit coupled to the coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of points stored by the memory and in response to the same coefficients, and d) an output circuit coupled to the transform circuit and generating the transformed output signals in response to the plurality of transformed points.

Claim 51

A transform processor system as set forth in claim 41, wherein the translation input circuit is an incremental translation input circuit generating the translation driving function signal as an incremental translation driving function signal and wherein the rotation input circuit is an incremental rotation input circuit generating the rotation driving function signal as an incremental rotation driving function signal.

Claim 52

A transform processor system as set forth in claim 41, wherein the translation input circuit is an incremental translation input circuit generating the translation driving function signal as an incremental translation driving function signal and wherein the rotation input circuit is an incremental rotation input circuit generating the rotation driving function signal as an incremental rotation driving function signal and wherein the coefficient processor is an incremental coefficient processor generating the plurality of coefficients by incrementally processing the incremental translation driving function signal and the incremental rotation driving function signal.

Claim 53

A transform processor system as set forth in claim 41, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 54

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; an object coefficient processor generating object transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the object coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the object transform coefficients; a second transform processor coupled to the object coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same object transform coefficients as used for the generation of the first transform point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 55

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; an object coefficient processor generating object transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the object coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the object transform coefficients; a second transform processor coupled to the object coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same object transform coefficients as used for the generation of the first transform point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 56

A transform processor system as set forth in claim 45, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 57

A transform processor system as set forth in claim 45, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the object coefficient processor is an incremental object coefficient processor generating the object transform coefficients by incrementally processing the incremental driving function signal.

Claim 58

A transform processor system as set forth in claim 45, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the object coefficient processor is an incremental object coefficient processor generating the object transform coefficients by incrementally processing the incremental driving function signal, wherein the first transform processor is a first incremental transform processor generating the first transformed point by incrementally processing the first one of the plurality of input points stored by the memory in response to the object transform coefficients, and wherein the second transform processor is a second incremental transform processor generating the second transformed point by incrementally processing the second one of the plurality of input points stored by the memory in response to the same object transform coefficients.

Claim 59

A transform processor system as set forth in claim 45, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 60

A transform processor system as set forth in claim 45, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the object coefficient processor generates the object transform coefficients in response to the rotation driving function command signal and in, response to the translation driving function command signal.

Claim 61

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; an object coefficient processor generating a plurality of object coefficients in response to the driving function signal; a transform processor coupled to the object coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same object coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 62

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; an object coefficient processor generating a plurality of object coefficients in response to the driving function signal; a transform processor coupled to the object coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same object coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 63

A transform processor system as set forth in claim 51, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 64

A transform processor system as set forth in claim 51, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the object coefficient processor is an incremental object coefficient processor generating the plurality of object coefficients by incrementally processing the incremental driving function signal.

Claim 65

A transform processor system as set forth in claim 51, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the object coefficient processor is an incremental object coefficient processor generating the plurality of object coefficients by incrementally processing the incremental driving function signal, and wherein the transform processor is an incremental transform processor generating the plurality of transformed points by incrementally processing the plurality of input points stored by the memory in response to the same object coefficients.

Claim 66

A transform processor system as set forth in claim 51, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 67

A transform processor system as set forth in claim 51, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the object coefficient processor generates the plurality of object coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 68

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a surface coefficient processor generating surface transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the surface coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the surface transform coefficients; a second transform processor coupled to the surface coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same surface transform coefficients as used for the generation of the first transformed point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 69

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a surface coefficient processor generating surface transform coefficients that are common to a plurality of input points in response to the driving function signal; a first transform processor coupled to the surface coefficient processor and to the memory and generating a first transformed point in response to a first one of the plurality of input points stored by the memory and in response to the surface transform coefficients; a second transform processor coupled to the surface coefficient processor and to the memory and generating a second transformed point in response to a second one of the plurality of input points stored by the memory and in response to the same surface transform coefficients as used for the generation of the first transformed point; and an output circuit coupled to the first transform processor and to the second transform processor and generating transformed output signals in response to the first transformed point and the second transformed point.

Claim 70

A transform processor system as set forth in claim 57, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 71

A transform processor system as set forth in claim 57, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the surface coefficient processor is an incremental surface coefficient processor generating the surface transform coefficients by incrementally processing the incremental driving function signal.

Claim 72

A transform processor system as set forth in claim 57, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the surface coefficient processor is an incremental surface coefficient processor generating the surface transform coefficients by incrementally processing the incremental driving function signal, wherein the first transform processor is a first incremental transform processor generating the first transformed point by incrementally processing the first one of the plurality of input points stored by the memory in response to the surface transform coefficients, and wherein the second transform processor is a second incremental transform processor generating the second transformed point by incrementally processing the second one of the plurality of input points stored by the memory in response to the same surface transform coefficients.

Claim 73

A transform processor system as set forth in claim 57, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 74

A transform processor system as set forth in claim 57, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the surface coefficient processor generates the surface transform coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 75

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a surface coefficient processor generating a plurality of surface coefficients in response to the driving function signal; a transform processor coupled to the surface coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same surface coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 76

A transform processor system comprising: an input circuit generating a driving function signal; a memory storing a plurality of input points, each input point having a plurality of parameters; a surface coefficient processor generating a plurality of surface coefficients in response to the driving function signal; a transform processor coupled to the surface coefficient processor and to the memory and generating a plurality of transformed points in response to the plurality of input points stored by the memory and in response to the same surface coefficients; and an output circuit coupled to the transform processor and generating transformed output signals in response to the plurality of transformed points.

Claim 77

A ransform processor system as set forth in claim 63, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal.

Claim 78

A transform processor system as set forth in claim 63, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal and wherein the surface coefficient processor is an incremental surface coefficient processor generating the plurality of surface coefficients by incrementally processing the incremental driving function signal.

Claim 79

A transform processor system as set forth in claim 63, wherein the input circuit is an incremental input circuit generating the driving function signal as an incremental driving function signal, wherein the surface coefficient processor is an incremental surface coefficient processor generating the plurality of surface coefficients by incrementally processing the incremental driving function signal, and wherein the transform processor is an incremental transform processor generating the plurality of transformed points by incrementally processing the plurality of input points stored by the memory in response to the same surface coefficients.

Claim 80

A transform processor system as set forth in claim 63, further comprising an operator display coupled to the output circuit and generating an operator display in response to the transformed output signals.

Claim 81

A transform processor system as set forth in claim 63, wherein the input circuit includes a rotation device generating a rotation driving function command signal and a translation device generating a translation driving function command signal, wherein the surface coefficient processor generates the plurality of surface coefficients in response to the rotation driving function command signal and in response to the translation driving function command signal.

Claim 82

In a transform processor system, a process comprising: generating a driving function signal; storing a plurality of input points, each input point having a plurality of parameters; generating a plurality of coefficients in response to the driving function signal; generating a plurality of transformed points in response to the plurality of stored input points and in response to the same coefficients; and generating transformed output signals in response to the plurality of transformed points.

Claim 83

In a transform processor system, a process comprising: generating a driving function signal; storing a plurality of input points, each input point having a plurality of parameters; generating a plurality of coefficients in response to the driving function signal; generating a plurality of transformed points in response to the plurality of stored input points and in response to the same coefficients; and generating transformed output signals in response to the plurality of transformed points.

Claim 84

In a transform processor system, a process comprising: generating a driving function signal; storing a plurality of input points, each input point having a plurality of parameters; generating a plurality of hierarchal coefficients in response to the driving function signal; generating a plurality of transformed points in response to the plurality of input points and in response to the same hierarchal coefficients; and generating transformed output signals in response to the plurality of transformed points.

Claim 85

In a transform processor system, a process comprising: generating a driving function signal; storing a plurality of input points, each input point having a plurality of parameters; generating a plurality of hierarchal coefficients in response to the driving function signal; generating a plurality of transformed points in response to the plurality of input points and in response to the same hierarchal coefficients; and generating transformed output signals in response to the plurality of transformed points.

Claim 86

In a transform processor system, a process comprising: storing a plurality of input points, each input point having a plurality of parameters; generating driving function signals related to the input points stored by the memory; generating detector signals indicative of changes in the driving function signals; transforming the input points in response to the detector signals; and generating transformed output signals in response to the transformed input points.

Claim 87

In a transform processor system, a process comprising: storing a plurality of input points, each input point having a plurality of parameters; generating driving function signals related to the input points stored by the memory; generating detector signals indicative of changes in the driving function signals; transforming the input points in response to the detector signals; and generating transformed output signals in response to the transformed input points.

Claim 88

In a transform processor system, a process comprising: storing a plurality of input points, each input point having a plurality of parameters; generating driving function signals related to the input points stored by the memory; generating detector signals indicative of changes in the driving function signals; transforming the input points when the detector signals are indicative of changes in the driving function signals and bypassing transforming of the input points when the detector signals are indicative of no change in the driving function signals; and generating transformed output signals in response to the transformed input points.

Claim 89

In a transform processor system, a process comprising: storing a plurality of input points, each input point having a plurality of parameters; generating driving function signals related to the input points stored by the memory; generating detector signals indicative of changes in the driving function signals; transforming the input points when the detector signals are indicative of changes in the driving function signals and bypassing transforming of the input points when the detector signals are indicative of no change in the driving function signals; and generating transformed output signals in response to the transformed input points.