US5682161A
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High-order delta sigma modulator
Assignee: General Electric Co
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Filing: 1996-05-20
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Granted: 1997-10-28
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Expires: 2016-05-20
Abstract
Abstract A delta-sigma modulator includes, in one embodiment, cascaded unit-delay integrators, the number of which is selected depending upon the order desired. The modulator further includes an n-bit (or multi-bit) A/D converter coupled to the output of the last cascaded integrator, and an n-bit (or multi-bit) D/A converter coupled to the output of the A/D converter. A truncator also is coupled to the output of the A/D converter. Truncation error correction is performed digitally by a truncation corrector. A one-bit D/A converter provides feedback from the output of the truncator to differential summing junctions interposed at the input of each unit-delay integrator. The multi-bit D/A converter output signal is fed back to differential summing junctions at the input of the third order and higher unit-delay integrators. The multi-bit D/A converter requires no digital correction of its linearity and only unit-delay integrators are used so that N-1 delay free integrators do not all have to settle within one clock period. The modulator therefore utilizes multiple quantizer bits to provide increased converter resolution and is stable at high orders.
Inventors
- 👤 David Byrd Ribner
- 👤 David Henry Kenneth Hoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:14
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/422; H03M3/424; H03M3/428; H03M3/436; H03M3/438; H03M3/454
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
304 words
An oversampled interpolative modulator for receiving an input analog signal and generating an output digital signal, said modulator comprising: a plurality of cascaded integrators for generating an integrated analog output signal, said plurality of cascaded integrators including: a first summation junction for receiving an input analog signal and subtractively adding a first voltage to generate a first difference output signal; a first unit-delay integrator coupled to the output of said first summation junction for integrating the first difference output signal; a second summation junction for receiving an analog output signal from said first unit-delay integrator and subtractively adding a second voltage to generate a second difference output signal; a second unit-delay integrator coupled to the output of said second summation junction for integrating the second difference output signal; a third summation junction for receiving an analog output signal from said second unit-delay integrator and subtractively adding a third voltage to generate a third difference output signal; a fourth summation junction for receiving an analog output signal from said third summation junction and subtractively adding a fourth voltage to generate a fourth difference output signal; and a third unit-delay integrator coupled to the output of said fourth summation junction for integrating the fourth difference output signal; a multi-bit analog-to-digital converter coupled to receive the integrated analog output signal from said plurality of cascaded integrators; a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the analog output of said multi-bit digital-to-analog converter being coupled to said fourth summation junction; a truncator coupled to the output of said multi-bit analog-to-digital converter; and a one-bit digital-to-analog converter coupled to the output of said truncator for converting the digital output signal of said truncator to an analog signal, the output of said one-bit digital-to-analog converter being coupled to said first, second and third summation junctions.
Claim 2
Dependent Claim
304 words
An oversampled interpolative modulator for receiving an input analog signal and generating an output digital signal, said modulator comprising: a plurality of cascaded integrators for generating an integrated analog output signal, said plurality of cascaded integrators including: a first summation junction for receiving an input analog signal and subtractively adding a first voltage to generate a first difference output signal; a first unit-delay integrator coupled to the output of said first summation junction for integrating the first difference output signal; a second summation junction for receiving an analog output signal from said first unit-delay integrator and subtractively adding a second voltage to generate a second difference output signal; a second unit-delay integrator coupled to the output of said second summation junction for integrating the second difference output signal; a third summation junction for receiving an analog output signal from said second unit-delay integrator and subtractively adding a third voltage to generate a third difference output signal; a fourth summation junction for receiving an analog output signal from said third summation junction and subtractively adding a fourth voltage to generate a fourth difference output signal; and a third unit-delay integrator coupled to the output of said fourth summation junction for integrating the fourth difference output signal; a multi-bit analog-to-digital converter coupled to receive the integrated analog output signal from said plurality of cascaded integrators; a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the analog output of said multi-bit digital-to-analog converter being coupled to said fourth summation junction; a truncator coupled to the output of said multi-bit analog-to-digital converter; and a one-bit digital-to-analog converter coupled to the output of said truncator for converting the digital output signal of said truncator to an analog signal, the output of said one-bit digital-to-analog converter being coupled to said first, second and third summation junctions.
Claim 3
Dependent Claim
51 words
The oversampled interpolative modulator of claim 1, further comprising a fifth summation junction coupled to receive the output of said multi-bit analog-to-digital converter and the output of said truncator, the output of said fifth summation junction being coupled to a truncation corrector for digitally correcting the error due to said truncator.
Claim 4
Dependent Claim
29 words
The oversampled interpolative modulator of claim 2, further comprising a sixth summation junction coupled to the output of said truncation corrector and the output of said multi-bit analog-to-digital converter.
Claim 5
Dependent Claim
32 words
The oversampled interpolative modulator of claim 1 wherein said first unit-delay integrator employs a first scaling factor k 1 and said second unit-delay integrator employs a second scaling factor k 2 .
Claim 6
Dependent Claim
83 words
The oversampled interpolative modulator of claim 4 further comprising a fifth summation junction coupled to receive the output of said multi-bit analog-to-digital converter and the output of said truncator, the output of said fifth summation junction being coupled to a truncation corrector for digitally correcting error due to said truncator by using the output of said fifth summation junction, said modulator further comprising a sixth summation junction coupled to the output of said truncation corrector and the output of said multi-bit analog-to-digital converter.
Claim 7
Dependent Claim
361 words
A delta sigma analog-to-digital converter comprising: an oversampled interpolative modulator for receiving an input analog signal to be converted and generating an output digital signal; a digital filter coupled to receive the output digital signal of said oversampled interpolative modulator for generating a filtered digital output signal; and a decimator coupled to receive the filtered digital output signal of said digital filter for reducing the sampling rate of said filtered digital output signal, said oversampled interpolative modulator comprising: a plurality of cascaded integrators for generating an integrated analog output signal, said plurality of cascaded integrators including: a first summation junction for receiving an input analog signal and subtractively adding a first voltage to generate a first difference output signal; a first unit-delay integrator coupled to the output of said first summation junction for integrating the first difference output signal; a second summation junction for receiving an analog output signal from said first unit-delay integrator and subtractively adding a second voltage to generate a second difference output signal; a second unit-delay integrator coupled to the output of said second summation junction for integrating the second difference output signal; a third summation junction for receiving an analog output signal from said second unit-delay integrator and subtractively adding a third voltage to generate a third difference output signal; a fourth summation junction for receiving an analog output signal from said third summation junction and subtractively adding a fourth voltage to generate a fourth difference output signal; a third unit-delay integrator coupled to the output of said fourth summation junction for integrating the fourth difference output signal; a multi-bit analog-to-digital converter coupled to receive the integrated analog output signal from said plurality of cascaded integrators; a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the output of said multi-bit digital-to-analog converter being coupled to said fourth summation junction; a truncator coupled to the output of said multi-bit analog-to-digital converter; and a one-bit digital-to-analog converter coupled to the output of said truncator for converting the digital output signal of said truncator to an analog signal, the output of said one-bit digital-to-analog converter being coupled to said first, second and third summation junctions.
Claim 8
Dependent Claim
361 words
A delta sigma analog-to-digital converter comprising: an oversampled interpolative modulator for receiving an input analog signal to be converted and generating an output digital signal; a digital filter coupled to receive the output digital signal of said oversampled interpolative modulator for generating a filtered digital output signal; and a decimator coupled to receive the filtered digital output signal of said digital filter for reducing the sampling rate of said filtered digital output signal, said oversampled interpolative modulator comprising: a plurality of cascaded integrators for generating an integrated analog output signal, said plurality of cascaded integrators including: a first summation junction for receiving an input analog signal and subtractively adding a first voltage to generate a first difference output signal; a first unit-delay integrator coupled to the output of said first summation junction for integrating the first difference output signal; a second summation junction for receiving an analog output signal from said first unit-delay integrator and subtractively adding a second voltage to generate a second difference output signal; a second unit-delay integrator coupled to the output of said second summation junction for integrating the second difference output signal; a third summation junction for receiving an analog output signal from said second unit-delay integrator and subtractively adding a third voltage to generate a third difference output signal; a fourth summation junction for receiving an analog output signal from said third summation junction and subtractively adding a fourth voltage to generate a fourth difference output signal; a third unit-delay integrator coupled to the output of said fourth summation junction for integrating the fourth difference output signal; a multi-bit analog-to-digital converter coupled to receive the integrated analog output signal from said plurality of cascaded integrators; a multi-bit digital-to-analog converter coupled to the output of said multi-bit analog-to-digital converter, the output of said multi-bit digital-to-analog converter being coupled to said fourth summation junction; a truncator coupled to the output of said multi-bit analog-to-digital converter; and a one-bit digital-to-analog converter coupled to the output of said truncator for converting the digital output signal of said truncator to an analog signal, the output of said one-bit digital-to-analog converter being coupled to said first, second and third summation junctions.
Claim 9
Dependent Claim
63 words
The delta sigma analog-to-digital converter of claim 6 wherein said oversampled interpolative modulator further comprises a fifth summation junction coupled to the output of said multi-bit analog-to-digital converter and the output of said truncator, the output of said fifth summation junction coupled to a truncation corrector for digitally correcting error due to said truncator by using the output of said fifth summation junction.
Claim 10
Dependent Claim
35 words
The delta sigma analog-to-digital converter of claim 7 wherein said oversampled interpolative modulator further comprises a sixth summation junction coupled to the output of said truncation corrector and the output of said multi-bit analog-to-digital converter.
Claim 11
Dependent Claim
39 words
The delta sigma analog-to-digital converter of claim 8 wherein said first unit-delay integrator comprises a first scaled integrator of scaling factor k l and said second unit-delay integrator comprises a second scaled integrator of scaling factor k 2 .
Claim 12
Dependent Claim
89 words
The delta sigma analog-to-digital converter of claim 9 wherein said oversampled interpolative modulator further comprises a fifth summation junction coupled to receive the output of said multi-bit analog-to-digital converter and the output of said truncator, the output of said fifth summation junction being coupled to a truncator conrrector for correcting error due to said truncator by using the output of said fifth summation junction, said modulator further comprising a sixth summation junction coupled to the output of said truncation error corrector and the output of said multi-bit analog-to-digital converter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-27 | 2001-04-28 | 2001-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-27 | 2005-04-28 | 2005-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-27 | 2009-04-28 | 2009-10-28 | $7700.00 | Window Closed / Lapsed |