US5187482A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delta sigma analog-to-digital converter with increased dynamic range
Assignee: General Electric Co
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Filing: 1992-03-02
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Granted: 1993-02-16
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Expires: 2012-03-02
Abstract
Abstract A delta sigma analog-to-digital (A/D) converter includes a digitally-controlled multiplying digital-to-analog converter (MDAC) in a feedback configuration. The MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter. An incremental feedback quantum to the first stage integrator is a function of the input values that immediately precede it. In the most general implementation, a table look-up permits an arbitrary relation between the input values and feedback quantum size. In another implementation, the A/D converter output (or intermediate output) signal drive the MDAC and the compression curve of the A/D converter bears a square-root relationship to the input analog signal; a linear relationship is restored by squaring the output signal. In a third implementation, the MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter together with an added small positive constant number. In this implementation, the compression curve starts out approximately linear and approaches a square-root relationship at the high end of the scale, while a linear relationship is restored by providing the feedback loop, in the digital domain, with the same value of signal as employed in the analog domain.
Inventors
- 👤 Jerome J. Tiemann
- 👤 Steven L. Garverick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:09
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/458; H03M3/476; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/436; H03M3/438; H03M3/454
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A delta sigma analog-to-digital converter comprising: an oversampled interpolative modulator for receiving an input analog signal to be converted and generating an output digital signal; digital filter means coupled to receive the output digital signal of said oversampled interpolative modulator for generating a filtered digital output signal; and a decimator coupled to receive the filtered digital output signal of said digital filter for compressing the sampling rate of said filtered digital output signal; said oversampled interpolative modulator comprising: summing means for receiving said input analog signal and subtractively adding a voltage to generate a difference output signal; at least one integrator coupled to said summing means for integrating said difference output signal; comparator means coupled to said at least one integrator for generating a digital "one" or "zero" depending on whether the integrator output signal exceeds a predetermined threshold; and a digitally controlled multiplying digitalto-analog converter coupled to the output of said digital filter means and selectively coupled to either of a positive and negative reference voltage, and being responsive to a digital control signal derived, at least in part, from an output of said digital filter means.
Claim 2
Dependent Claim
188 words
A delta sigma analog-to-digital converter comprising: an oversampled interpolative modulator for receiving an input analog signal to be converted and generating an output digital signal; digital filter means coupled to receive the output digital signal of said oversampled interpolative modulator for generating a filtered digital output signal; and a decimator coupled to receive the filtered digital output signal of said digital filter for compressing the sampling rate of said filtered digital output signal; said oversampled interpolative modulator comprising: summing means for receiving said input analog signal and subtractively adding a voltage to generate a difference output signal; at least one integrator coupled to said summing means for integrating said difference output signal; comparator means coupled to said at least one integrator for generating a digital "one" or "zero" depending on whether the integrator output signal exceeds a predetermined threshold; and a digitally controlled multiplying digitalto-analog converter coupled to the output of said digital filter means and selectively coupled to either of a positive and negative reference voltage, and being responsive to a digital control signal derived, at least in part, from an output of said digital filter means.
Claim 3
Dependent Claim
72 words
The delta sigma analog-to-digital converter recited in claim 1 further comprising table look-up means coupling the output of said digital filter means to said multiplying digital-to-analog converter, for receiving as an address an output signal of said digital filter means and reading out data representing feedback quantum size to said multiplying digital-to-analog converter so as to thereby permit an arbitrary relation between the input analog signal values and the feedback quantum size.
Claim 4
Dependent Claim
27 words
The delta sigma analog-to-digital converter recited in claim 2 wherein said table look-up means comprises a static random access memory loaded with data by an external computer.
Claim 5
Dependent Claim
48 words
The delta sigma analog-to-digital converter recited in claim 1 wherein the analog-to-digital converter exhibits a compression curve bearing a square-root relationship to the input analog signal and further comprises multiplier means coupled to the output of said decimator for squaring the output signal of said digital filter means.
Claim 6
Dependent Claim
19 words
The delta sigma analog-to-digital converter recited in claim 4 wherein said digital filter means comprises a short digital filter.
Claim 7
Dependent Claim
105 words
The delta sigma analog-to-digital converter recited in claim 1 further comprising: summing means coupled to the output of said digital filter means for adding an offset value to the filtered digital output signal and providing a digital sum output signal, said digital sum output signal being directly supplied to said multiplying digital-to-analog converter, whereby the analog-to-digital converter exhibits a compression curve that starts out approximately linear and approaches a square-root relationship with respect to the input analog signal; and gating means for passing filtered digital signals from the output of said summing means to said decimator in response to output signals of said comparator means.
Claim 8
Dependent Claim
24 words
The delta sigma analog-to-digital converter recited in claim 6 further including a decimation filter coupling the output of said gating means to said decimator.
Claim 9
Dependent Claim
23 words
The delta sigma analog-to-digital converter recited in claim 1 wherein said oversampled interpolative modulator is a second order modulator comprising two cascaded integrators.
Claim 10
Dependent Claim
23 words
The delta sigma analog-to-digital converter recited in claim 1 wherein said oversampled interpolative modulator is a first order modulator comprising a single integrator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-02-16 | 1996-08-17 | 1997-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-02-16 | 2000-08-17 | 2001-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-02-16 | 2004-08-17 | 2005-02-16 | $7700.00 | Window Closed / Lapsed |