Method for forming isolated intra-polycrystalline silicon structure

Claim 1

A portion of a multiple layer integrated circuit device, comprising: first and second field effect transistors in a substrate, each field effect transistor having a gate formed from a first patterned layer of polycrystalline silicon and source/drain regions formed in the substrate; a first oxide layer over the field effect transistors and the substrate; an opening through the first oxide layer in a contact region, wherein a source/drain region of the first field effect transistor is exposed in the opening; a second layer of patterned polycrystalline silicon over the first oxide layer and in the opening to make contact with the exposed source/drain region; a second layer of oxide over the second polycrystalline silicon layer and the first oxide layer; a third layer over the second oxide layer, wherein first portions of the third layer are polycrystalline silicon and second portions of the third layer are an insulating material formed from polycrystalline of the third layer, and wherein the first portions of the third layer define a patterned interconnect which includes source/drain and channel regions having been formed by implanted impurities.