US5680178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video multiplexing system for superimposition of scalable video data streams upon a background video data stream
Assignee: Seiko Epson Corp
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Filing: 1995-05-26
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Granted: 1997-10-21
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Expires: 2015-05-26
Abstract
Abstract A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.
Inventors
- 👤 Kesatoshi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:47
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/16; G09G1/165; G09G1/167; G09G5/00; G09G5/14; G09G5/36; G09G5/39; G09G5/395; H; H04; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/414; H04N21/4143; H04N5/00; H04N5/44; H04N5/445; H04N5/44504; H04N5/45; H04N9/00; H04N9/64; H04N9/641; G09G2340/00; G09G2340/04; G09G2340/0407; G09G2340/0435; G09G2340/12; G09G2340/125; G09G2360/00; G09G2360/02; G09G2360/12; G09G2360/126; G09G5/001; G09G5/003; G09G5/006; G09G5/008; G09G5/363; G09G5/393; H04N21/426
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
249 words
An image control device for use in a computer system having a microprocessor, a bus coupled to said microprocessor, a video memory coupled to said bus, and a display device, said image control device comprising: write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals; and read control means coupled to said bus for supplying said video switch with a first selection signal to instruct said selecting, and controlling the reading of said first image signal out of said video memory by supplying a read address to said video memory asynchronously with said writing into said video memory and in synchronism with a synchronizing signal which is to be supplied to said display device along with said image signal read out of said video memory; wherein said read control means comprises: means for changing a range of said read address according to a plurality of read address parameters set by said microprocessor so that a memory area of said video memory from which said image signal is to be read out is changed according to said range of said read address; and means for changing a size of an image represented by said image signal read out of said video memory.
Claim 2
Dependent Claim
249 words
An image control device for use in a computer system having a microprocessor, a bus coupled to said microprocessor, a video memory coupled to said bus, and a display device, said image control device comprising: write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals; and read control means coupled to said bus for supplying said video switch with a first selection signal to instruct said selecting, and controlling the reading of said first image signal out of said video memory by supplying a read address to said video memory asynchronously with said writing into said video memory and in synchronism with a synchronizing signal which is to be supplied to said display device along with said image signal read out of said video memory; wherein said read control means comprises: means for changing a range of said read address according to a plurality of read address parameters set by said microprocessor so that a memory area of said video memory from which said image signal is to be read out is changed according to said range of said read address; and means for changing a size of an image represented by said image signal read out of said video memory.
Claim 3
Dependent Claim
85 words
An image control device in accordance with claim 1, wherein said write control means comprises: means for changing a range of said write address according to a plurality of write address parameters set by said microprocessor so that a memory area of said video memory into which said image signal is to be written is changed according to said range of said write address; and means for changing a size of an image represented by said image signal to be written into said video memory.
Claim 4
Dependent Claim
27 words
An image control device in accordance with claim 2, further comprising: an input buffer for temporarily storing said image signal to be written into said video memory.
Claim 5
Dependent Claim
78 words
An image control device in accordance with claim 3, further comprising: a first output buffer, coupled to said video memory and said display device, for temporarily storing said image signal read out of said video memory before transferring said image signal to said display device; and a second output buffer, coupled to said video memory and said microprocessor, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.
Claim 6
Dependent Claim
236 words
A computer system comprising: a microprocessor; a bus coupled to said microprocessor; a video memory coupled to said bus; a display device; write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals; and read control means coupled to said bus for supplying said video switch with a first selection signal to instruct said selecting, and controlling the reading of said first image signal out of said video memory by supplying a read address to said video memory asynchronously With said writing into said video memory and in synchronism with a synchronizing signal which is to be supplied to said display device along with said image signal read out of said video memory; wherein said read control means comprises: means for changing a range of said read address according to a plurality of read address parameters set by said microprocessor so that a memory area of said video memory from which said image signal is to be read out is changed according to said range of said read address; and means for changing a size of an image represented by said image signal read out of said video memory.
Claim 7
Dependent Claim
236 words
A computer system comprising: a microprocessor; a bus coupled to said microprocessor; a video memory coupled to said bus; a display device; write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals; and read control means coupled to said bus for supplying said video switch with a first selection signal to instruct said selecting, and controlling the reading of said first image signal out of said video memory by supplying a read address to said video memory asynchronously With said writing into said video memory and in synchronism with a synchronizing signal which is to be supplied to said display device along with said image signal read out of said video memory; wherein said read control means comprises: means for changing a range of said read address according to a plurality of read address parameters set by said microprocessor so that a memory area of said video memory from which said image signal is to be read out is changed according to said range of said read address; and means for changing a size of an image represented by said image signal read out of said video memory.
Claim 8
Dependent Claim
84 words
A computer system in accordance with claim 5, wherein said write control means comprises: means for changing a range of said write address according to a plurality of write address parameters set by said microprocessor so that a memory area of said video memory into which said image signal is to be written is changed according to said range of said write address; and means for changing a size of an image represented by said image signal to be written into said video memory.
Claim 9
Dependent Claim
26 words
A computer system in accordance with claim 6, further comprising: an input buffer for temporarily storing said image signal to be written into said video memory.
Claim 10
Dependent Claim
77 words
A computer system in accordance with claim 7, further comprising: a first output buffer, coupled to said video memory and said display device, for temporarily storing said image signal read out of said video memory before transferring said image signal to said display device; and a second output buffer, coupled to said video memory and said microprocessor, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |