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US5679592A
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Process for formation of LDD MOSFET wing photoresist
Assignee: Chung Cheng Holding LLC
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Filing: 1995-12-18
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Granted: 1997-10-21
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Expires: 2015-12-18
Abstract
Abstract A process for forming a MOSFET, which includes the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming lightly doped impurity regions on the left and right sides of the gate electrode and on the substrate; spreading photoresist, and forming a photoresist pattern for defining a side wall spacer formation portion on the gate electrode and on sides of the gate electrode; depositing an insulating layer on the surface of the substrate, and etching the insulating layer to remove an exposed surface portion and to form a side wall spacer on sides of the gate electrode; and removing the photoresist pattern, and forming a heavily doped source/drain region on the gate electrode and on sides of the side wall.
Inventors
- 👤 Ho-young Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0147; H10D30/022; H10D30/0221; H10D30/0227; H10D30/60; H10D30/601; H10D30/603
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
128 words
A process for forming an MOS transistor, comprising the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming lightly doped impurity regions on left and right sides of the gate electrode in the substrate; applying photoresist, and patterning the photoresist to form an open portion at the sides of the gate electrode, wherein the photoresist is removed from the open portion; depositing and etching an insulating layer, wherein an exposed surface portion of the insulating layer is etched, wherein a side wall spacer is formed at the sides of the gate electrode in the open portion; and removing the photoresist pattern, and forming a heavily doped source/drain region in the substrate beside the side wall spacer of the gate electrode.
Claim 2
Dependent Claim
128 words
A process for forming an MOS transistor, comprising the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming lightly doped impurity regions on left and right sides of the gate electrode in the substrate; applying photoresist, and patterning the photoresist to form an open portion at the sides of the gate electrode, wherein the photoresist is removed from the open portion; depositing and etching an insulating layer, wherein an exposed surface portion of the insulating layer is etched, wherein a side wall spacer is formed at the sides of the gate electrode in the open portion; and removing the photoresist pattern, and forming a heavily doped source/drain region in the substrate beside the side wall spacer of the gate electrode.
Claim 3
Dependent Claim
23 words
The process of claim 1, wherein the insulating layer comprises an oxide layer formed by applying a low temperature chemical vapor deposition method.
Claim 4
Dependent Claim
20 words
The process of claim 2, wherein the oxide layer is formed by maintaining a process temperature below about 150° Celsius.
Claim 5
Dependent Claim
17 words
The process of claim 1, wherein the insulating layer is etched by applying a wet etching method.
Claim 6
Dependent Claim
18 words
The process of claim 4, wherein, in carrying out the wet etching method, a fluoride solution is used.
Claim 7
Dependent Claim
14 words
The process of claim 5, wherein the fluoride solution is a buffered HF acid.
Claim 8
Dependent Claim
18 words
The process of claim 1, wherein, the photoresist is patterned using a chemical capable of removing organic materials.
Claim 9
Dependent Claim
27 words
The process of claim 7, wherein the chemical capable of removing organic materials comprises a mixture of H 2 SO 4 and H 2 O 2 .
Claim 10
Dependent Claim
17 words
The process of claim 1, wherein the side wall spacer is symmetrical relative to the gate electrode.
Claim 11
Dependent Claim
17 words
The process of claim 1, wherein the side wall spacer is asymmetrical relative to the gate electrode.
Claim 12
Dependent Claim
131 words
A process for forming an MOS transistor, comprising the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming first doped impurity regions at sides of the gate electrode in the substrate; forming a side wall spacer formation pattern, wherein the side wall spacer formation pattern includes an open portion at one or more sides of the gate electrode, wherein the side wall spacer formation pattern is not formed in the open portion; forming an insulating layer in the open portion, wherein the insulating layer forms a side wall spacer at the side of the gate electrode in the open portion; and removing the side wall spacer formation pattern, and forming a second doped impurity region in the substrate beside the side wall spacer.
Claim 13
Dependent Claim
131 words
A process for forming an MOS transistor, comprising the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming first doped impurity regions at sides of the gate electrode in the substrate; forming a side wall spacer formation pattern, wherein the side wall spacer formation pattern includes an open portion at one or more sides of the gate electrode, wherein the side wall spacer formation pattern is not formed in the open portion; forming an insulating layer in the open portion, wherein the insulating layer forms a side wall spacer at the side of the gate electrode in the open portion; and removing the side wall spacer formation pattern, and forming a second doped impurity region in the substrate beside the side wall spacer.
Claim 14
Dependent Claim
33 words
The process of claim 11, wherein the step of forming a side wall spacer formation pattern comprises forming a photoresist layer and patterning the photoresist layer to form the sidewall formation layer pattern.
Claim 15
Dependent Claim
42 words
The process of claim 11, wherein the step of forming an insulating layer in the open portion comprising forming the insulating layer and etching a portion of the insulating layer, wherein a portion of the insulating layer remains in the open portion.
Claim 16
Dependent Claim
23 words
The process of claim 11, wherein the insulating layer comprises an oxide layer formed by applying a low temperature chemical vapor deposition method.
Claim 17
Dependent Claim
20 words
The process of claim 14, wherein the oxide layer is formed by maintaining a process temperature below about 150° Celsius.
Claim 18
Dependent Claim
18 words
The process of claim 11, wherein the side wall spacer is formed without utilizing an anisotropic etch process.
Claim 19
Dependent Claim
17 words
The process of claim 13, wherein the insulating layer is etched by applying a wet etching method.
Claim 20
Dependent Claim
43 words
The process of claim 11, wherein an open portion is formed at first and second sides of the gate electrode, wherein first and second side wall spacers are formed in the open portions at the first and second sides of the gate electrode.
Claim 21
Dependent Claim
16 words
The process of claim 18, wherein the first and second side wall spacers have equal widths.
Claim 22
Dependent Claim
16 words
The process of claim 18, wherein the first and second side wall spacers have unequal widths.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |