US5677868A
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US
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Batch erasable nonvolatile memory device and erasing method
Assignee: Renesas Electronics Corp
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Filing: 1996-10-31
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Granted: 1997-10-14
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Expires: 2016-10-31
Abstract
Abstract A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
Inventors
- 👤 Masahito Takahashi
- 👤 Michiko Odagiri
- 👤 Takeshi Furuno
- 👤 Kazunori Furusawa
- 👤 Masashi Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3477; G11C16/10; G11C16/14; G11C16/16; G11C16/3404; G11C16/3409; G11C16/344; G11C16/3445
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
267 words
A nonvolatile memory device comprising: a plurality of blocks, each block comprising a word line, a plurality of data lines and a plurality of memory cells, said plurality of memory cells storing information as values of a threshold voltage; a selecting unit selecting at least one block of the plurality of blocks; a command decoder decoding a command supplied thereto; and a control circuit controlling a specified operation according to a result of decoding by said command decoder, wherein each of said plurality of memory cells has a floating gate, and wherein said control circuit controls execution of a first ejecting operation, an injecting operation and a second ejecting operation in accordance with a result of decoding of a command indicating a threshold voltage changing operation by said command decoder, in which (i) said first ejecting operation is for ejecting electrons from the floating gates and setting a threshold voltage of said plurality of memory cells in said selected at least one block to be lower than a first voltage, (ii) said injecting operation is for injecting electrons into the floating gates to set the threshold voltage of the memory cells, which is determined higher than 0V and lower than a second voltage which is lower than said first voltage, to be higher than said second voltage after said first ejecting operation is performed, and (iii) said second ejecting operation is for ejecting electrons from the floating gates to set the threshold voltage of said plurality of memory cells in said selected at least one block to be higher than 0V after said injecting operation is performed.
Claim 2
Dependent Claim
267 words
A nonvolatile memory device comprising: a plurality of blocks, each block comprising a word line, a plurality of data lines and a plurality of memory cells, said plurality of memory cells storing information as values of a threshold voltage; a selecting unit selecting at least one block of the plurality of blocks; a command decoder decoding a command supplied thereto; and a control circuit controlling a specified operation according to a result of decoding by said command decoder, wherein each of said plurality of memory cells has a floating gate, and wherein said control circuit controls execution of a first ejecting operation, an injecting operation and a second ejecting operation in accordance with a result of decoding of a command indicating a threshold voltage changing operation by said command decoder, in which (i) said first ejecting operation is for ejecting electrons from the floating gates and setting a threshold voltage of said plurality of memory cells in said selected at least one block to be lower than a first voltage, (ii) said injecting operation is for injecting electrons into the floating gates to set the threshold voltage of the memory cells, which is determined higher than 0V and lower than a second voltage which is lower than said first voltage, to be higher than said second voltage after said first ejecting operation is performed, and (iii) said second ejecting operation is for ejecting electrons from the floating gates to set the threshold voltage of said plurality of memory cells in said selected at least one block to be higher than 0V after said injecting operation is performed.
Claim 3
Dependent Claim
39 words
The nonvolatile memory device according to claim 1, wherein each of said plurality of memory cells further has a control gate over which said floating gate is formed and a pair of semiconductor regions formed under said floating gate.
Claim 4
Dependent Claim
42 words
The nonvolatile memory device according to claim 2, further comprising a voltage generator circuit generating said first and second voltages, on the basis of a power supply voltage applied thereto, during a verify operation associated with said first and second ejecting operations.
Claim 5
Dependent Claim
47 words
The nonvolatile memory device according to claim 3, wherein each of said plurality of word lines is coupled with a control gate of corresponding memory cells, and said first and second voltages are applied to a word line in a selected one of said plurality of blocks.
Claim 6
Dependent Claim
96 words
The nonvolatile memory device according to claim 4, wherein a difference between an internal voltage to be applied to said control gate of the memory cell and an internal voltage to be applied to one of said pair of semiconductor regions in said first ejecting operation is larger than a difference between an internal voltage to be applied to said control gate and an internal voltage to be applied to said one of said pair of semiconductor regions in said second ejecting operation, in those ones of memory cells in said selected at least one block.
Claim 7
Dependent Claim
21 words
The nonvolatile memory device according to claim 5, wherein said one of pair of said semiconductor regions is a source region.
Claim 8
Dependent Claim
31 words
The nonvolatile memory device according to claim 6, wherein electrons in each of said floating gates are ejected to each of the source regions in said first and second ejecting operations.
Claim 9
Dependent Claim
21 words
The nonvolatile memory device according to claim 5, wherein said one of pair of said semiconductor regions is a drain region.
Claim 10
Dependent Claim
31 words
The nonvolatile memory device according to claim 8, wherein electrons in each of said floating gates are ejected to each of the drain regions in said first and second ejecting operations.
Claim 11
Dependent Claim
75 words
The nonvolatile memory device according to claim 4, wherein a time in which internal voltages are applied to said control gate and to one of said pair of semiconductor regions in said first ejecting operation is different from a time in which internal voltages are applied to said control gate and to said one of said pair of semiconductor regions in said second ejecting operation, of memory cells in said selected at least one block.
Claim 12
Dependent Claim
19 words
The nonvolatile memory device according to claim 1, wherein the memory device is a single chip nonvolatile semiconductor device.
Claim 13
Dependent Claim
231 words
A nonvolatile memory device comprising: a plurality of blocks, each comprising a word line, a plurality of data lines and a plurality of memory cells, said plurality of memory cells storing information as values of a threshold voltage; a selecting unit selecting at least one block of the plurality of blocks; a command decoder decoding a command supplied; and a control circuit controlling a specified operation according to a result of decoding by said command decoder, wherein each of said plurality of memory cells has a floating gate, and wherein said control circuit controls execution of a first ejecting operation, a verify operation and a threshold voltage setting operation in accordance with a result of decoding of a command indicating a threshold voltage changing operation by said command decoder, in which (i) said first ejecting operation is for ejecting electrons from the floating gates, (ii) said verify operation is for verifying whether a threshold voltage of each of said plurality of memory cells in a selected block is set into a predetermined range which is higher than 0V and which is lower than a first voltage, and (iii) said threshold voltage setting operation is for setting only a threshold voltage of outside of said predetermined range into said predetermined range when a memory cell having a threshold voltage of said outside of said predetermined range is verified in said verify operation.
Claim 14
Dependent Claim
231 words
A nonvolatile memory device comprising: a plurality of blocks, each comprising a word line, a plurality of data lines and a plurality of memory cells, said plurality of memory cells storing information as values of a threshold voltage; a selecting unit selecting at least one block of the plurality of blocks; a command decoder decoding a command supplied; and a control circuit controlling a specified operation according to a result of decoding by said command decoder, wherein each of said plurality of memory cells has a floating gate, and wherein said control circuit controls execution of a first ejecting operation, a verify operation and a threshold voltage setting operation in accordance with a result of decoding of a command indicating a threshold voltage changing operation by said command decoder, in which (i) said first ejecting operation is for ejecting electrons from the floating gates, (ii) said verify operation is for verifying whether a threshold voltage of each of said plurality of memory cells in a selected block is set into a predetermined range which is higher than 0V and which is lower than a first voltage, and (iii) said threshold voltage setting operation is for setting only a threshold voltage of outside of said predetermined range into said predetermined range when a memory cell having a threshold voltage of said outside of said predetermined range is verified in said verify operation.
Claim 15
Dependent Claim
27 words
The nonvolatile memory device according to claim 12, wherein each of said plurality of memory cells further has a control gate, and a pair of semiconductor regions.
Claim 16
Dependent Claim
32 words
The nonvolatile memory device according to claim 13, wherein said electrons in the floating gate are ejected to one of said pair of semiconductor regions in said first and second ejecting operation.
Claim 17
Dependent Claim
92 words
The nonvolatile memory device according to claim 14, wherein a difference between an internal voltage to be applied to said control gate and an internal voltage to be applied to one of said pair of semiconductor regions in said first ejecting operation is different from a difference between an internal voltage to be applied to said control gate and an internal voltage to be applied to said one of said pair of semiconductor regions in said second ejecting operation, in those ones of memory cells in said selected at least one block.
Claim 18
Dependent Claim
75 words
The nonvolatile memory device according to claim 15, wherein a time in which internal voltages are applied to said control gate and to one of said pair of semiconductor regions in said first ejecting operation is different from a time in which internal voltages are applied to said control gate and to said one of said pair of semiconductor regions in said second ejecting operation, of memory cells in said selected at least one block.
Claim 19
Dependent Claim
75 words
The nonvolatile memory device according to claim 14, wherein a time in which internal voltages are applied to said control gate and to one of said pair of semiconductor regions in said first ejecting operation is different from a time in which internal voltages are applied to said control gate and to said one of said pair of semiconductor regions in said second ejecting operation, of memory cells in said selected at least one block.
Claim 20
Dependent Claim
19 words
The nonvolatile memory device according to claim 15, wherein the memory device is a single chip nonvolatile semiconductor device.
Claim 21
Dependent Claim
19 words
The nonvolatile memory device according to claim 12, wherein the memory device is a single chip nonvolatile semiconductor device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |