Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus

Claim 1

A recording and reproducing apparatus comprising: a recording medium having a recorded test recording signal thereon; read means for reading out said test recording signal from said recording medium; a phase locked loop circuit for generating a clock signal with a phase synchronized to said test recording signal read out from said recording medium, said phase locked loop circuit including a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to said voltage controlled oscillator, an AD-conversion circuit for sampling said test recording signal with a timing determined by said clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of said digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting said control data into a first analog signal and for outputting said first analog signal to said voltage controlled oscillator as said voltage control signal; demodulation means for demodulating data of said test recording signal read out by said read means using said clock signal to generate playback data; and control means including means for controlling said read means to read out from said recording medium said test recording signal of a predetermined test pattern data recorded on said recording medium, means for controlling said demodulation means to reproduce test playback data from the predetermined test pattern data of said test recording signal read by said read means, means for comparing said test playback data to said predetermined test pattern data, means for determining whether or not contents of said test playback data are erroneous, and means for adjusting the conversion characteristic of said DA-conversion circuit based at least on a result of the determination whether or not the contents of the test playback data are erroneous.

Claim 22

A method for adjusting a phase locked loop circuit having a voltage controlled oscillator, an AD-conversion circuit, a phase locked loop control circuit and a DA-conversion circuit with an adjustable conversion characteristic, comprising the steps of: generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator; sampling an input signal with timing determined by the clock signal and converting sampled values into digital data by the AD-conversion circuit; generating control data with values representing values of the digital data by the phase locked loop circuit; converting the control data into an analog signal by the DA-conversion circuit with the adjustable conversion characteristic and outputting the analog signal to the voltage controlled oscillator as the voltage control signal; changing the adjustable conversion characteristic of the DA-conversion circuit to predetermined values; supplying the input signal having a known normal reproduced result of said changed conversion characteristics to the phase locked loop circuit; causing the phase locked loop circuit to generate the clock signal; reproducing data from the input signal in accordance with the generated clock signal; comparing the reproduced data to the known normal reproduced result; determining an optimum conversion characteristic for the DA-conversion circuit from results of comparison for a plurality of individual predetermined values; and setting the optimum conversion characteristic in the DA-conversion circuit.

Claim 23

A method for adjusting a phase locked loop circuit having a voltage controlled oscillator, an AD-conversion circuit, a phase locked loop control circuit and a DA-conversion circuit with an adjustable conversion characteristic, comprising the steps of: generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator; sampling an input signal with timing determined by the clock signal and converting sampled values into digital data by the AD-conversion circuit; generating control data with values representing values of the digital data by the phase locked loop circuit; converting the control data into an analog signal by the DA-conversion circuit with the adjustable conversion characteristic and outputting the analog signal to the voltage controlled oscillator as the voltage control signal; changing the adjustable conversion characteristic of the DA-conversion circuit to predetermined values; supplying the input signal having a known normal reproduced result of said changed conversion characteristics to the phase locked loop circuit; causing the phase locked loop circuit to generate the clock signal; reproducing data from the input signal in accordance with the generated clock signal; comparing the reproduced data to the known normal reproduced result; determining an optimum conversion characteristic for the DA-conversion circuit from results of comparison for a plurality of individual predetermined values; and setting the optimum conversion characteristic in the DA-conversion circuit.