Process of fabricating semiconductor integrated circuit device having small geometry contact by using spacer on photoresist mask

Claim 2

A process of fabricating a semiconductor device, comprising the steps of: a) preparing a target layer of first material to be patterned; b) forming a photo-resist layer on said target layer; c) transferring a pattern to said photo-resist layer so as to form at least one first opening defined by an inner surface of said photo-resist layer and exposing a part of said target layer; d) depositing a spacer layer of second material so as to cover an upper surface of said photo-resist layer, said inner surface of said photo-resist layer and said part of said target layer, said spacer layer defining a cavity narrower than said at least one opening; and e) exposing said spacer layer and said target layer to a first anisotropical etchant having little selectivity between said first material and said second material so as to etch said spacer layer and said target layer by a continuous etching process in a single process step and form a second opening in said target layer smaller in area than said at least one first opening.

Claim 3

The process as set forth in claim 1, in which said first material and said second material are silicon oxide.

Claim 4

The process as set forth in claim 2, in which said silicon oxide is deposited through an atmospheric pressure chemical vapor deposition using tetraethoxy-fluoro-silane in said step d).

Claim 5

The process as set forth in claim 1, in which a thickness of said photo-resist layer is close to a thickness of said target layer.

Claim 6

The process as set forth in claim 1, in which said target layer is laminated on a mask layer of a third material, and said mask layer is laminated on a patternable layer of a fourth material, said first anisotropical etchant having a large selectivity between said third material and said second material, said process further comprising the steps of: f) removing said photo-resist layer; g) anisotropically etching said mask layer by using said target layer as an etching mask so as to form a third opening not wider than said second opening and exposing a part of said patternable layer; and h) exposing at least said part of said patternable layer to a second anisotropical etchant having a large selectivity between said third material and said fourth material so as to form a fourth opening in said patternable layer.

Claim 7

The process as set forth in claim 5, in which said first material, said second material and said fourth material are silicon oxide, and said third material is polysilicon.

Claim 8

A process of fabricating a semiconductor device, comprising the steps of: a) preparing a semiconductor substrate overlain by a inter-level insulating layer of silicon oxide; b) forming a photo-resist layer approximately equal in thickness to said inter-level insulating layer on said inter-level insulating layer; c) transferring a pattern image to said photo-resist layer so as to form a first opening in said photo-resist layer; d) depositing a spacer layer of silicon oxide through an atmospheric pressure chemical vapor deposition using tetraethoxy-fluoro-silane so as to cover an upper surface of said photo-resist layer, an inner surface of said photo-resist layer defining said first opening and a part of said inter-level insulating layer exposed to said first opening therewith, said spacer layer defining a second opening narrower than said first opening; and e) anisotropically etching said spacer layer and said part of said inter-level insulating layer by a continuous etching process in a single process step, so as to form a contact hole in said inter-level insulating layer which is narrower than said first opening.

Claim 9

A process of fabricating a semiconductor device, comprising the steps of: a) preparing a semiconductor substrate overlain by a inter-level insulating layer of silicon oxide; b) forming a photo-resist layer approximately equal in thickness to said inter-level insulating layer on said inter-level insulating layer; c) transferring a pattern image to said photo-resist layer so as to form a first opening in said photo-resist layer; d) depositing a spacer layer of silicon oxide through an atmospheric pressure chemical vapor deposition using tetraethoxy-fluoro-silane so as to cover an upper surface of said photo-resist layer, an inner surface of said photo-resist layer defining said first opening and a part of said inter-level insulating layer exposed to said first opening therewith, said spacer layer defining a second opening narrower than said first opening; and e) anisotropically etching said spacer layer and said part of said inter-level insulating layer by a continuous etching process in a single process step, so as to form a contact hole in said inter-level insulating layer which is narrower than said first opening.

Claim 10

A process of fabricating a semiconductor device, comprising the steps of: a) preparing a multi-level structure on a semiconductor substrate, said multi-level structure having an inter-level insulating layer of silicon oxide laminated on said semiconductor substrate, a polysilicon layer laminated on said inter-level insulating layer and a first silicon oxide layer laminated on said polysilicon layer; b) forming a photo-resist layer approximately equal in thickness to said first silicon oxide layer and laminated on said first silicon oxide layer; c) transferring a pattern image on said photo-resist layer so as to form a first opening in said photo-resist layer; d) depositing a second silicon oxide layer through an atmospheric pressure chemical vapor deposition using tetraethoxy-fluoro-silane so as to cover an upper surface of said photo-resist layer, an inner surface of said photo-resist layer defining said first opening and a part of said first silicon oxide layer exposed to said first opening therewith, said second silicon oxide layer defining a second opening narrower than said first opening; e) anisotropically etching said second silicon oxide layer and said part of said first silicon oxide layer by a continuous etching process in a single process step, so as to form a third opening in said first silicon oxide layer which is narrower than said first opening, a part of said polysilicon layer being exposed to said third opening; f) removing said photo-resist layer; g) anisotropically etching said part of said polysilicon layer so as to form a fourth opening narrower than said first opening in said polysilicon layer, a part of said inter-level insulating layer being exposed to said fourth opening; h) anisotropically etching said part of said inter-level insulating layer so as to form a fifth opening narrower than said first opening in said inter-level insulating layer; and i) removing said polysilicon layer.

Claim 11

A process of fabricating a semiconductor device, comprising the steps of: a) preparing a multi-level structure on a semiconductor substrate, said multi-level structure having an inter-level insulating layer of silicon oxide laminated on said semiconductor substrate, a polysilicon layer laminated on said inter-level insulating layer and a first silicon oxide layer laminated on said polysilicon layer; b) forming a photo-resist layer approximately equal in thickness to said first silicon oxide layer and laminated on said first silicon oxide layer; c) transferring a pattern image on said photo-resist layer so as to form a first opening in said photo-resist layer; d) depositing a second silicon oxide layer through an atmospheric pressure chemical vapor deposition using tetraethoxy-fluoro-silane so as to cover an upper surface of said photo-resist layer, an inner surface of said photo-resist layer defining said first opening and a part of said first silicon oxide layer exposed to said first opening therewith, said second silicon oxide layer defining a second opening narrower than said first opening; e) anisotropically etching said second silicon oxide layer and said part of said first silicon oxide layer by a continuous etching process in a single process step, so as to form a third opening in said first silicon oxide layer which is narrower than said first opening, a part of said polysilicon layer being exposed to said third opening; f) removing said photo-resist layer; g) anisotropically etching said part of said polysilicon layer so as to form a fourth opening narrower than said first opening in said polysilicon layer, a part of said inter-level insulating layer being exposed to said fourth opening; h) anisotropically etching said part of said inter-level insulating layer so as to form a fifth opening narrower than said first opening in said inter-level insulating layer; and i) removing said polysilicon layer.

Claim 12

The process as set forth in claim 1, wherein said step of depositing said spacer layer is performed at no higher than 130 degrees centigrade.

Claim 13

The process as set forth in claim 1, wherein a type of material used for said first and said second material is selected so as to enable a single anisotropic etchant to be used for said anisotropical etchant having little selectivity between said first and said second material.

Claim 14

The process as set forth in claim 1, wherein said target layer is an inter-level insulating layer into which said second opening is formed, and said process further comprises the step of: forming a conductive material in said second opening, said conductive material being a contact plug between an area of said semiconductor substrate and a conductive layer formed over said inter-level insulating layer.

Claim 15

The process as set forth in claim 1, wherein said first anisotropical etchant contains fluorine.

Claim 16

The process as set forth in claim 7, wherein said step of depositing said spacer layer is performed at no higher than 130 degrees centigrade.

Claim 17

The process as set forth in claim 7, further comprising the step of: forming a conductive material in said contact hole, said conductive material being a contact plug between an area of said semiconductor substrate and a conductive layer formed over said inter-level insulating layer.

Claim 18

The process as set forth in claim 7, wherein said step of anisotropically etching said second silicon oxide layer and said part of said inter-level insulating layer is performed with an etchant containing fluorine.

Claim 19

The process as set forth in claim 8, wherein said step of depositing said second silicon oxide layer is performed at no higher than 130 degrees centigrade.

Claim 20

The process as set forth in claim 8, wherein said step of anisotropically etching said second silicon oxide layer and said part of said first oxide layer is performed with an etchant containing fluorine.