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US5677220A
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Method of manufacturing a semiconductor device
Assignee: Panasonic Holdings Corp
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Filing: 1995-06-07
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Granted: 1997-10-14
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Expires: 2015-06-07
Abstract
Abstract A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed. With the second insulating layer of such configuration, an increase in connection resistance and a connection defect of the capacity storage electrode contact or the bit line contact are prevented.
Inventors
- 👤 Tomofumi Shono
- 👤 Akira Asai
- 👤 Masanori Fukumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:39
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
243 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation which defines a semiconductor substrate into a plurality of active regions at which a MISFET of a DRAM memory cell is to be formed; forming a word line and a first insulating layer which covers said word line at a region including at least a part of each active region of said semiconductor substrate; forming a first diffusion region and a second diffusion region by introducing an impurity to each active region, said first diffusion region and said second diffusion region functioning as a source or drain; forming a second insulating layer, by depositing an insulating film on each active region, said first insulating layer and the isolation, removing a part of the insulating film including in common each overhead region in contact with at least two second diffusion regions out of the diffusion regions in the active regions and an isolation disposed between said two second diffusion regions, leaving another part of said insulating film including at least an overhead region in contact with said first diffusion region; and forming, above said second diffusion region in each active region, a conductive member and a contact member that connects said conductive member and said second diffusion region by depositing a conductive film entirely over the substrate and then removing a part of said conductive film, leaving a part of said conductive film in contact with said second diffusion region.
Claim 2
Independent Claim
243 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an isolation which defines a semiconductor substrate into a plurality of active regions at which a MISFET of a DRAM memory cell is to be formed; forming a word line and a first insulating layer which covers said word line at a region including at least a part of each active region of said semiconductor substrate; forming a first diffusion region and a second diffusion region by introducing an impurity to each active region, said first diffusion region and said second diffusion region functioning as a source or drain; forming a second insulating layer, by depositing an insulating film on each active region, said first insulating layer and the isolation, removing a part of the insulating film including in common each overhead region in contact with at least two second diffusion regions out of the diffusion regions in the active regions and an isolation disposed between said two second diffusion regions, leaving another part of said insulating film including at least an overhead region in contact with said first diffusion region; and forming, above said second diffusion region in each active region, a conductive member and a contact member that connects said conductive member and said second diffusion region by depositing a conductive film entirely over the substrate and then removing a part of said conductive film, leaving a part of said conductive film in contact with said second diffusion region.
Claim 3
Dependent Claim
91 words
The method of manufacturing a semiconductor device according to claim 1, wherein a drain region of said MISFET of said DRAM memory cell is formed as said first diffusion region, wherein a source region of said MISFET of the DRAM memory cell is formed as said second diffusion region, wherein a capacity storage electrode is formed as said conductive member, and wherein a capacity storage electrode contact which connects said capacity storage electrode and said source region of said MISFET of said DRAM memory cell is formed as the contact member.
Claim 4
Dependent Claim
49 words
The method of manufacturing a semiconductor device according to claim 2, wherein at said step for forming said second insulating layer, a region including in common each overhead region on a plurality of source regions arranged in parallel with said word line is removed out of the insulating film.
Claim 5
Dependent Claim
52 words
The method of manufacturing a semiconductor device according to claim 2, wherein at said step for forming said second insulating layer, a region including in common each overhead region on a plurality of source regions arranged across at a right angle to said word line is removed out of the insulating film.
Claim 6
Dependent Claim
75 words
The method of manufacturing a semiconductor device according to claim 2, further comprising the steps of: forming a peripheral circuit of said DRAM memory cell: forming a conductive layer on said capacity storage electrode; and forming a plate electrode, wherein said step for forming said second insulating layer is conducted so that the removed region of said second insulating layer is located inside of a region at which said plate electrode is to be formed.
Claim 7
Dependent Claim
95 words
The method of manufacturing a semiconductor device according to claim 1, wherein a gate electrode of said MISFET of said DRAM memory cell is formed as a wiring member, wherein a source region of said MISFET of said DRAM memory cell is formed as said first diffusion region, wherein a drain region of said MISFET of said DRAM memory cell is formed as said second diffusion region, wherein a bit line is formed as said conductive member, and wherein a bit line contact which connects the bit line and is formed as said contact member.
Claim 8
Dependent Claim
49 words
The method of manufacturing a semiconductor device according to claim 6, wherein at said step for forming said second insulating layer, a region including in common each overhead region on a plurality of drain regions arranged substantially in parallel with said wiring member forming said gate electrode is removed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |