US5673427A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
Assignee: Intel Corp
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Filing: 1996-07-03
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Granted: 1997-09-30
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Expires: 2016-07-03
Abstract
Abstract A micro-operation queue for holding a plurality of micro-operations supplied simultaneously by a decoder. A plurality of packing multiplexers are coupled to receive the plurality of micro-operations, and valid bits associated therewith, and to provide packed micro-operation data output in which the valid micro-operations are positioned in adjacent outputs, thereby removing all empty slots. A FIFO queue receives the packed data, in responsive to valid micro-operations, stores the valid micro-operations starting with the next available empty queue location. An embodiment described in which the FIFO queue includes a circular queue with a plurality of entries. In one embodiment, alignment multiplexers for the circular queue are combined with the packing multiplexers, to provide a single-level plurality of packing and aligning multiplexers that has a control system that, responsive to the valid bits of the packed data and the next available pointer of the circular queue, packs, aligns, and stores the micro-operations into the circular queue from where they can be issued.
Inventors
- 👤 Gary L. Brown
- 👤 Adrian L. Carbine
- 👤 Donald D. Parker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/22; G06F9/28; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/3004; G06F9/38; G06F9/3824; G06F9/383
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
135 words
A system for queuing micro-operations supplied from a macroinstruction decoder in a processor, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the system comprising: packing circuitry coupled to receive a plurality of micro-operations from the decoder, and configured to identify a set of valid micro-operations, indicated to be valid by the states of the respective valid bits, and to output the set of valid micro-operations as a set of adjacent outputs, so as to pack the set of valid micro-operations; and a memory circuit comprising a plurality of entries in which to maintain a queue of micro-operations, the memory circuit being coupled to receive the set of valid micro-operations from the packing circuitry into adjacent entries of the memory circuit.
Claim 2
Independent Claim
135 words
A system for queuing micro-operations supplied from a macroinstruction decoder in a processor, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the system comprising: packing circuitry coupled to receive a plurality of micro-operations from the decoder, and configured to identify a set of valid micro-operations, indicated to be valid by the states of the respective valid bits, and to output the set of valid micro-operations as a set of adjacent outputs, so as to pack the set of valid micro-operations; and a memory circuit comprising a plurality of entries in which to maintain a queue of micro-operations, the memory circuit being coupled to receive the set of valid micro-operations from the packing circuitry into adjacent entries of the memory circuit.
Claim 3
Dependent Claim
83 words
The system of claim 1 wherein the packing circuitry comprises: a plurality of selectors, each coupled to receive a plurality of micro-operations from the decoder, and operable to output a selected micro-operation; and packing control circuitry configured to identify the set of valid micro-operations indicated to be valid by the states of the respective valid bits, and to operate the selectors to output the set of valid micro-operations from a set of adjacent selectors, so as to pack the set of valid micro-operations.
Claim 4
Dependent Claim
26 words
The system of claim 2 wherein each of the plurality of selectors comprises a packing multiplexer coupled to receive the plurality of micro-operations from the decoder.
Claim 5
Dependent Claim
59 words
The system of claim 1 wherein a target entry of the memory circuit is designated as a next available location, and the system includes alignment circuitry coupled to receive the set of valid micro-operations from the packing circuitry, and configured to align a first micro-operation of the set of valid micro-operations with the target entry of the memory circuit.
Claim 6
Dependent Claim
33 words
The system of claim 4 wherein the alignment circuitry is configured to determine whether a sufficient number of adjacent entries of the memory circuit are available to accommodate the set of valid micro-instructions.
Claim 7
Dependent Claim
79 words
The system of claim 4 wherein the alignment circuitry comprises: a plurality of alignment multiplexers, each of which is coupled to receive a selected micro-operation from each of the respective selectors and operable to output an aligned micro-operation; and alignment control circuitry configured to identify the target entry of the memory circuit, and to operate the plurality of alignment multiplexers to output the first micro-operation of the set of valid micro-operations to the target entry of the memory circuit.
Claim 8
Dependent Claim
61 words
The system of claim 1 wherein the plurality of entries of the memory circuit comprises a set of adjacent entries having a first entry and a last entry, the memory circuit maintaining a circular queue of micro-operations by regarding the first entry of the plurality of entries as proceeding, and being adjacent to, the last entry of the plurality of entries.
Claim 9
Independent Claim
191 words
A system for queuing micro-operations supplied from a macroinstruction decoder in a processor, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the system comprising: a plurality of selectors, each coupled to receive a plurality of micro-operations from the decoder, and operable to output a selected micro-operation; a memory circuit comprising a plurality of entries in which to maintain a queue of micro-operations, a target entry of the memory being designated as the next available location, each entry of the memory circuit being coupled to receive a selected micro-operation from a corresponding selector; and control circuitry configured to identify: a set of valid micro-operations indicated to be valid by the states of the respective valid bits; and the target entry of the memory circuit; and to operate the selectors to output the set of valid micro-operations: from a set of adjacent selectors, so as to pack the set of valid micro-operations; and so that the first micro-operation of the set of valid micro-operations is outputted from the selector corresponding to the target entry of the memory circuit.
Claim 10
Independent Claim
191 words
A system for queuing micro-operations supplied from a macroinstruction decoder in a processor, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the system comprising: a plurality of selectors, each coupled to receive a plurality of micro-operations from the decoder, and operable to output a selected micro-operation; a memory circuit comprising a plurality of entries in which to maintain a queue of micro-operations, a target entry of the memory being designated as the next available location, each entry of the memory circuit being coupled to receive a selected micro-operation from a corresponding selector; and control circuitry configured to identify: a set of valid micro-operations indicated to be valid by the states of the respective valid bits; and the target entry of the memory circuit; and to operate the selectors to output the set of valid micro-operations: from a set of adjacent selectors, so as to pack the set of valid micro-operations; and so that the first micro-operation of the set of valid micro-operations is outputted from the selector corresponding to the target entry of the memory circuit.
Claim 11
Dependent Claim
26 words
The system of claim 8 wherein each of the plurality of selectors comprises a packing multiplexer coupled to receive the plurality of micro-operations from the decoder.
Claim 12
Dependent Claim
33 words
The system of claim 8 wherein the control circuitry is configured to determine whether a sufficient number of adjacent entries of the memory circuit are available to accommodate the set of valid micro-instructions.
Claim 13
Dependent Claim
62 words
The system of claim 8 wherein the plurality of entries of the memory circuit comprise a consecutive set of entries having a first entry and a last entry, and the memory circuit maintains a circular queue of micro-operations by regarding the first entry of the plurality of entries as proceeding, and being adjacent to, the last entry of the plurality of entries.
Claim 14
Independent Claim
156 words
A method of propagating micro-operations from a decoder of a processor to a queue maintained within a memory circuit, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the memory circuit comprising a plurality of entries in which to maintain the queue and having a target entry designated as the next available location, the method comprising the steps of: issuing a plurality of micro-operations from the decoder; examining the valid bit associated with each of the plurality of micro-operations to identify a set of valid micro-operations; packing the set of valid micro-operations by propagating the set of valid micro-operations to a set of consecutive entries in the memory circuit; identifying the target entry of the memory circuit; and aligning the set of valid operations by presenting a first micro-operation of the set of valid micro-operations to the target entry of memory circuit.
Claim 15
Independent Claim
156 words
A method of propagating micro-operations from a decoder of a processor to a queue maintained within a memory circuit, each micro-operation having a valid bit associated therewith, the state of the valid bit indicating whether the respective micro-operation is valid or invalid, the memory circuit comprising a plurality of entries in which to maintain the queue and having a target entry designated as the next available location, the method comprising the steps of: issuing a plurality of micro-operations from the decoder; examining the valid bit associated with each of the plurality of micro-operations to identify a set of valid micro-operations; packing the set of valid micro-operations by propagating the set of valid micro-operations to a set of consecutive entries in the memory circuit; identifying the target entry of the memory circuit; and aligning the set of valid operations by presenting a first micro-operation of the set of valid micro-operations to the target entry of memory circuit.
Claim 16
Dependent Claim
41 words
The method of claim 12 including the step determining whether a sufficient number of consecutive entries of the memory circuit are available to accommodate the set of valid micro-operations and, if so, receiving the set of valid micro-operations within the memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |