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US5673409A
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Self-defining instruction size
Assignee: NXP BV
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Filing: 1993-03-31
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Granted: 1997-09-30
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Expires: 2013-03-31
Abstract
Abstract A method and apparatus for defining, in a computing system, the bit size of an instruction to be executed by a processing unit. Instructions are realized in the form of a plurality of memory location devices. At least one of said memory location devices, in a predetermined position, is established as a MODE bit. The MODE bit assumes a first value indicative of parallel instruction execution and assumes a second value indicative of non-parallel instruction execution.
Inventors
- 👤 Gary Dwayne Hicok
- 👤 Thomas Alexander
- 👤 Yong Je Lim
- 👤 Yongmin Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3853; G06F9/30145; G06F9/30149; G06F9/30152; G06F9/30181; G06F9/30185
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
146 words
A method for defining a size of an instruction to be executed by a processing unit, the method comprising the steps: (a) storing a plurality of instructions in a memory storage means, each of said plurality of instructions comprising a number of bits; (b) establishing a single bit location in a predetermined bit location in each of said plurality of instructions, said single bit being a MODE bit which has a first value indicating parallel execution wherein a current instruction is executed in parallel with a successive instruction and a second value indicating non-parallel execution wherein said current instruction is executed by itself; and (c) reading said MODE bit in each of said plurality of instructions to determine if said current instruction is to be executed in parallel manner with said successive instruction or if said current instruction is to be executed in a non-parallel manner.
Claim 2
Independent Claim
146 words
A method for defining a size of an instruction to be executed by a processing unit, the method comprising the steps: (a) storing a plurality of instructions in a memory storage means, each of said plurality of instructions comprising a number of bits; (b) establishing a single bit location in a predetermined bit location in each of said plurality of instructions, said single bit being a MODE bit which has a first value indicating parallel execution wherein a current instruction is executed in parallel with a successive instruction and a second value indicating non-parallel execution wherein said current instruction is executed by itself; and (c) reading said MODE bit in each of said plurality of instructions to determine if said current instruction is to be executed in parallel manner with said successive instruction or if said current instruction is to be executed in a non-parallel manner.
Claim 3
Dependent Claim
17 words
A method as defined in claim 1 wherein the first value and the second value are binary.
Claim 4
Dependent Claim
47 words
The method of claim 1 wherein said step of establishing a single bit location in a predetermined bit location in each of said plurality of instructions further comprises the step of establishing a MODE bit in a last bit location in each of said plurality of instructions.
Claim 5
Dependent Claim
87 words
In a computing system having a processor, a memory storage means storing a plurality of instructions, each of said plurality of instructions comprising a number of bits, wherein at least one bit in a predetermined location in each of said plurality of instructions contains MODE data, said MODE data having a first value indicative of parallel instruction execution wherein a current instruction is executed in parallel with a successive instruction and a second value indicative of non-parallel instruction execution wherein said current instruction is executed by itself.
Claim 6
Dependent Claim
87 words
In a computing system having a processor, a memory storage means storing a plurality of instructions, each of said plurality of instructions comprising a number of bits, wherein at least one bit in a predetermined location in each of said plurality of instructions contains MODE data, said MODE data having a first value indicative of parallel instruction execution wherein a current instruction is executed in parallel with a successive instruction and a second value indicative of non-parallel instruction execution wherein said current instruction is executed by itself.
Claim 7
Dependent Claim
20 words
A memory storage apparatus as defined in claim 4, wherein the first value and the second value are binary values.
Claim 8
Dependent Claim
24 words
The computing system of claim 4 wherein said MODE data is stored in a last bit location in each of said plurality of instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |