Patent US5673407A successfully refreshed from Google Patents.
US5673407A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor having capability to perform both floating point operations and memory access in response to a single instruction
Assignee: Texas Instruments Inc
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Filing: 1994-03-08
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Granted: 1997-09-30
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Expires: 2014-03-08
Abstract
Abstract A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.
Inventors
- 👤 Sydney W. Poland
- 👤 Christopher J. Read
- 👤 Karl M. Guttag
- 👤 Robert J. Gove
- 👤 Michael Gill
- 👤 Nicholas Ing Simmons
- 👤 Erick Oakland
- 👤 Jeremiah E. Golston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:28
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/012; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30025; G06F9/30036; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
184 words
A data processor comprising: an integer arithmetic logic unit performing integer and logical operations; a floating point unit performing floating point operations; a source of instructions, said source of instructions including at least one vector floating point instruction designating both a memory access and a floating point operation; at least one control register holding for storing a memory address; an instruction decode unit connected to said integer arithmetic logic unit, said floating point unit, said source of instructions and said at least one control register and responsive to instructions received from said source of instructions for controlling said operation of said data processing apparatus, said instruction decode unit responsive to a single received vector floating point instruction to perform a memory access employing said memory address stored in a control register designated by said single received vector floating point instruction, increment said address stored in said control register designated by said single received vector floating point instruction to address a next data word; and control said floating point unit to perform a floating point operation designated by said single received vector floating point instruction.
Claim 2
Dependent Claim
184 words
A data processor comprising: an integer arithmetic logic unit performing integer and logical operations; a floating point unit performing floating point operations; a source of instructions, said source of instructions including at least one vector floating point instruction designating both a memory access and a floating point operation; at least one control register holding for storing a memory address; an instruction decode unit connected to said integer arithmetic logic unit, said floating point unit, said source of instructions and said at least one control register and responsive to instructions received from said source of instructions for controlling said operation of said data processing apparatus, said instruction decode unit responsive to a single received vector floating point instruction to perform a memory access employing said memory address stored in a control register designated by said single received vector floating point instruction, increment said address stored in said control register designated by said single received vector floating point instruction to address a next data word; and control said floating point unit to perform a floating point operation designated by said single received vector floating point instruction.
Claim 3
Dependent Claim
59 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point add instruction designating a floating point add operation; and said instruction decode unit controls said floating point unit to add two floating point numbers in response to a received vector floating point add instruction.
Claim 4
Dependent Claim
98 words
The data processor of claim 2, further comprising: a plurality of floating point registers; said vector floating point add instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to add data recalled from said floating point register designated by said source register field to data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 5
Dependent Claim
59 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point subtract instruction designating a floating point subtract operation; and said instruction decoder unit control said floating point unit to subtract two floating point numbers in response to a received vector floating point subtract instruction.
Claim 6
Dependent Claim
98 words
The data processor of claim 4, further comprising: a plurality of floating point registers; said vector floating point subtract instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to subtract data recalled from said floating point register designated by said source register field from data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 7
Dependent Claim
58 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point multiply instruction designating a floating point multiply operation; and said instruction decode unit controls said floating point unit to multiply two floating point numbers in response to a received vector floating point multiply.
Claim 8
Dependent Claim
98 words
The data processor of claim 6, further comprising: a plurality of floating point registers; said vector floating point multiply instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to multiply data recalled from said floating point register designated by said source register field by data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 9
Dependent Claim
73 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point multiply and add instruction designating a floating point multiply and add operation; and said instruction decode unit controls said floating point unit to multiply two floating point numbers and add their product to a third floating point number in response to a vector floating point and multiply instruction.
Claim 10
Dependent Claim
110 words
The data processor of claim 8, further comprising: a plurality of floating point registers; an accumulator; said vector floating point multiply and add instruction includes a first source register field designating one of said floating point registers and a second source register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to multiply data recalled from said floating point register designated by said first source register field by data recalled from said floating point register designated by said second source register field, add a multiply result to data in stored in said accumulator and stores an add result in said accumulator.
Claim 11
Dependent Claim
73 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point multiply and subtract instruction designating a floating point multiply and subtract operation; and said instruction decode unit controls said floating point unit to multiply two floating point numbers and subtract their product from a third floating point number in response to a vector floating point and subtract instruction.
Claim 12
Dependent Claim
109 words
The data processor of claim 10, further comprising: a plurality of floating point registers; an accumulator; said vector floating point multiply and subtract instruction includes a first source register field designating one of said floating point registers and a second source register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to multiply data recalled from said floating point register designated by said first source register field by data recalled from said floating point register designated by said second source register field, subtract a multiply result from data stored in said accumulator and stores a subtract result in said accumulator.
Claim 13
Dependent Claim
68 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point conversion instruction designating a floating point format conversion operation; and said instruction decode unit controls said floating point unit to convert a first floating point number from a first format into a second format in response to a vector floating point conversion instruction.
Claim 14
Dependent Claim
37 words
The data processor of claim 12, wherein: said first and second formats are selected from the group consisting of an unsigned integer, a signed integer, a single precision floating point number and a double precision floating number.
Claim 15
Dependent Claim
91 words
The data processor of claim 12, further comprising: a plurality of floating point registers; said vector floating point add instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to recall data from said floating point register designated by said source register field, convert said recalled data into said second format and stores a result in said floating point register designated by said destination register field.
Claim 16
Dependent Claim
55 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point load instruction; and said memory access controlled by said instruction decoder in response to a vector floating point load instruction consists of a memory read recalling data from a memory.
Claim 17
Dependent Claim
113 words
The data processor of claim 15, further comprising: a plurality of floating point registers; said at least one control register includes at least one input pointer register and an output pointer register; said vector floating point load instruction includes a destination register field designating one of said floating point registers and an input pointer register field designating one of said at least one input pointer register; and said instruction decode unit controls said memory access to recall data from a memory at an address stored in an input pointer register designated by said input pointer register field and stores said recalled data in said floating point register designated by said destination register field.
Claim 18
Dependent Claim
70 words
The data processor of claim 16, wherein: said at least one input pointer register consists of a first input pointer register and a second input pointer register; and said input pointer register field consists of a single bit, a first state of said single bit designating said first input pointer register and a second state opposite to said first state of said single bit designating said second input pointer register.
Claim 19
Dependent Claim
51 words
The data processor of claim 15, further comprising: said vector floating point load instruction includes a data size field designating a data size to be loaded; and said instruction decode unit controls said memory access to recall data from a memory having a data size corresponding to said data size field.
Claim 20
Dependent Claim
69 words
The data processor of claim 18, wherein: said data size field of said vector floating point load instruction consists of a single bit; and said instruction decode unit controls said memory access to recall data from a memory having a first data size if said single bit has a first state and a second data size if said single bit has a second state opposite to said first state.
Claim 21
Dependent Claim
55 words
The data processor of claim 1, wherein: said at least one vector floating point instruction of said source of instructions includes a vector floating point conversion instruction; and said memory access controlled by said instruction decoder in response to a vector floating point store instruction consists of a memory write storing data into a memory.
Claim 22
Dependent Claim
90 words
The data processor of claim 20, further comprising: a plurality of floating point registers; said at least one control register includes at least one input pointer register and an output pointer register; said vector floating point store instruction includes a source register field designating one of said floating point registers; and said instruction decode unit controls said memory access to recall data from said floating point register designated by said source register field and stores said recalled data in a memory at an address stored in said output pointer register.
Claim 23
Dependent Claim
51 words
The data processor of claim 20, further comprising: said vector floating point store instruction includes a data size field designating a data size to be loaded; and said instruction decode unit controls said memory access to store data into a memory having a data size corresponding to said data size field.
Claim 24
Dependent Claim
69 words
The data processor of claim 22, wherein: said data size field of said vector floating point store instruction consists of a single bit; and said instruction decode unit controls said memory access to store data into a memory having a first data size if said single bit has a first state and a second data size if said single bit has a second state opposite to said first state.
Claim 25
Dependent Claim
222 words
A data processor comprising: a floating point unit including a floating point multiplier; a floating point arithmetic logic unit having an input multiplexed to an output of said floating point multiplier; and a pipeline control circuit for said floating point multiplier and said floating point arithmetic logic unit with pipeline stages for unpack, operate and normalize; memory circuitry; a source of instructions, said source of instructions including at least one vector floating point instruction designating both a floating point operation and a memory access; at least one control register holding for storing a memory address; and an instruction register and instruction logic circuitry connected to said floating point multiplier, said floating point arithmetic logic unit, said pipeline control circuit, said source of instructions and said at least one control register and responsive to a single vector floating point instruction received from said source of instructions to operate said floating point unit to perform said floating point operation designated by said single received vector floating point instruction and to perform a memory access employing said memory address stored in a control register designated by said received vector floating point instruction and incrementing said address stored in said control register designated by said single received vector floating point instruction to address a next data word concurrently with said operation of said floating point unit.
Claim 26
Dependent Claim
222 words
A data processor comprising: a floating point unit including a floating point multiplier; a floating point arithmetic logic unit having an input multiplexed to an output of said floating point multiplier; and a pipeline control circuit for said floating point multiplier and said floating point arithmetic logic unit with pipeline stages for unpack, operate and normalize; memory circuitry; a source of instructions, said source of instructions including at least one vector floating point instruction designating both a floating point operation and a memory access; at least one control register holding for storing a memory address; and an instruction register and instruction logic circuitry connected to said floating point multiplier, said floating point arithmetic logic unit, said pipeline control circuit, said source of instructions and said at least one control register and responsive to a single vector floating point instruction received from said source of instructions to operate said floating point unit to perform said floating point operation designated by said single received vector floating point instruction and to perform a memory access employing said memory address stored in a control register designated by said received vector floating point instruction and incrementing said address stored in said control register designated by said single received vector floating point instruction to address a next data word concurrently with said operation of said floating point unit.
Claim 27
Dependent Claim
25 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises a floating point add.
Claim 28
Dependent Claim
99 words
The data processor of claim 25, further comprising: a plurality of floating point registers; said vector floating point instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point arithmetic logic unit to add data recalled from said floating point register designated by said source register field to data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 29
Dependent Claim
25 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises a floating point subtract.
Claim 30
Dependent Claim
99 words
The data processor of claim 27, further comprising: a plurality of floating point registers; said vector floating point instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point arithmetic logic unit to subtract data recalled from said floating point register designated by said source register field from data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 31
Dependent Claim
25 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises a floating point multiply.
Claim 32
Dependent Claim
98 words
The data processor of claim 29, further comprising: a plurality of floating point registers; said vector floating point instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point multiply unit to multiply data recalled from said floating point register designated by said source register field by data recalled from said floating point register designated by said destination register field and stores a result in said floating point register designated by said destination register field.
Claim 33
Dependent Claim
26 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises floating point multiply and subtract.
Claim 34
Dependent Claim
115 words
The data processor of claim 31, further comprising: a plurality of floating point registers; an accumulator; said vector floating point instruction includes a first source register field designating one of said floating point registers and a second source register field designating one of said floating point registers; and said instruction decode unit controls said floating point multiply unit to multiply data recalled from said floating point register designated by said first source register field by data recalled from said floating point register designated by said second source register field, controls said floating point arithmetic logic unit to add a multiply result to data stored in said accumulator and stores an add result in said accumulator.
Claim 35
Dependent Claim
26 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises floating point multiply and add.
Claim 36
Dependent Claim
115 words
The data processor of claim 33, further comprising: a plurality of floating point registers; an accumulator; said vector floating point instruction includes a first source register field designating one of said floating point registers and a second source register field designating one of said floating point registers; and said instruction decode unit controls said floating point multiply unit to multiply data recalled from said floating point register designated by said first source register field by data recalled from said floating point register designated by said second source register field, control said floating point arithmetic logic unit to subtract a multiply result from data stored in said accumulator and stores a subtract result in said accumulator.
Claim 37
Dependent Claim
25 words
The data processor of claim 24 wherein said floating point operation designated by said single received vector floating point instruction comprises a floating point conversion.
Claim 38
Dependent Claim
90 words
The data processor of claim 35, further comprising: a plurality of floating point registers; said vector floating point instruction includes a source register field designating one of said floating point registers and a destination register field designating one of said floating point registers; and said instruction decode unit controls said floating point unit to recall data from said floating point register designated by said source register field, convert said recalled data into said second format and store a result in said floating point register designated by said destination register field.
Claim 39
Dependent Claim
46 words
The data processor of claim 24 wherein said floating point unit further includes plural accumulators for said floating point arithmetic logic unit, and said instruction logic is responsive to an instruction to select one of said accumulators for output from said floating point arithmetic logic unit.
Claim 40
Dependent Claim
27 words
The data processor of claim 24, wherein: said memory access operation controlled by said instruction logic circuitry consists of a memory read recalling data from a memory.
Claim 41
Dependent Claim
112 words
The data processor of claim 38, further comprising: a plurality of floating point registers; said at least one control register includes at least one input pointer register and an output pointer register; said vector floating point instruction includes a destination register field designating one of said floating point registers and an input pointer register field designating one of said at least one input pointer register; and said instruction decode unit controls said memory access to recall data from a memory at an address stored in an input pointer register designated by said input pointer register field and stores said recalled data in said floating point register designated by said destination register field.
Claim 42
Dependent Claim
70 words
The data processor of claim 39, wherein: said at least one input pointer register consists of a first input pointer register and a second input pointer register; and said input pointer register field consists of a single bit, a first state of said single bit designating said first input pointer register and a second state opposite to said first state of said single bit designating said second input pointer register.
Claim 43
Dependent Claim
50 words
The data processor of claim 38, further comprising: said vector floating point instruction includes a data size field designating a data size to be loaded; and said instruction decode unit controls said memory access to recall data from a memory having a data size corresponding to said data size field.
Claim 44
Dependent Claim
68 words
The data processor of claim 41, wherein: said data size field of said vector floating point instruction consists of a single bit; and said instruction decode unit controls said memory access to recall data from a memory having a first data size if said single bit has a first state and a second data size if said single bit has a second state opposite to said first state.
Claim 45
Dependent Claim
27 words
The data processor of claim 24, wherein: said memory access operation controlled by said instruction logic circuitry consists of a memory read recalling data from a memory.
Claim 46
Dependent Claim
89 words
The data processor of claim 43, further comprising: a plurality of floating point registers; said at least one control register includes at least one input pointer register and an output pointer register; said vector floating point instruction includes a source register field designating one of said floating point registers; and said instruction decode unit controls said memory access to recall data from said floating point register designated by said source register field and stores said recalled data in a memory at an address stored in said output pointer register.
Claim 47
Dependent Claim
50 words
The data processor of claim 43, further comprising: said vector floating point instruction includes a data size field designating a data size to be loaded; and said instruction decode unit controls said memory access to store data into a memory having a data size corresponding to said data size field.
Claim 48
Dependent Claim
69 words
The data processor of claim 45, wherein: said data size field of said vector floating point store instruction consists of a single bit; and said instruction decode unit controls said memory access to store data into a memory having a first data size if said single bit has a first state and a second data size if said single bit has a second state opposite to said first state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |