US5673398A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data transfer control method, and peripheral circuit, data processor and data processing system for the method
Assignee: Renesas Electronics Corp
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Filing: 1995-01-06
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Granted: 1997-09-30
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Expires: 2015-01-06
Abstract
Abstract A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
Inventors
- 👤 Hiroshi Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:55
CPC Classifications
A; A01; A01G; A01G13/00; A01G13/20; A01G13/27; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1027; B; B65; B65D; B65D31/00; B65D31/02; B65D33/00; B65D33/16; B65D33/30; B65D85/00; B65D85/30; B65D85/34; B65D85/50; B65D85/52; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G11C7/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
A method of controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the method comprising the steps of: sending an access request from the data processor to the memory, the access request including address signals; performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals; sending the second clock signals from the memory to the data processor; transferring data from the memory to the data processor in synchronism with the second clock signals; writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals; and, outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
Claim 2
Independent Claim
170 words
A method of controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the method comprising the steps of: sending an access request from the data processor to the memory, the access request including address signals; performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals; sending the second clock signals from the memory to the data processor; transferring data from the memory to the data processor in synchronism with the second clock signals; writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals; and, outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
Claim 3
Dependent Claim
83 words
The data transfer controlling method according to claim 1 wherein the access request includes a first signal for indicating a transfer direction of the data, said method further comprising the steps of: transferring the data from the data processor to the memory in synchronism with the second clock signals, when the first signal indicates the transfer direction as transferring the data from the data processor to the memory; and, writing the transferred data in the memory in synchronism with the second clock signals.
Claim 4
Dependent Claim
47 words
The data transfer controlling method according to claim 1 wherein the access request includes a second signal for indicating a burst mode in which a plurality of continuous data to be transferred in response to one access request are transferred in synchronism with the second clock signals.
Claim 5
Dependent Claim
47 words
The data transfer controlling method according to claim 2 wherein the access request includes a second signal for indicating a burst mode in which a plurality of continuous data to be transferred in response to one access request are transferred in synchronism with the second clock signals.
Claim 6
Dependent Claim
31 words
The data transfer controlling method according to claim 4 further comprising the step of: outputting a third signal for indicating completion of the data transfer after each of the transferring steps.
Claim 7
Independent Claim
180 words
An apparatus for controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the apparatus further comprising: means for sending an access request from the data processor to the memory, the access request including address signals; means for performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals; means for sending the second clock signals from the memory to the data processor; means for transferring data from the memory to the data processor in synchronism with the second clock signals; means for writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals; and, means for outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
Claim 8
Independent Claim
180 words
An apparatus for controlling a data transfer between a data processor operating in synchronism with first clock signals, the data processor having a buffer memory and an arithmetic circuit, and a memory operating in synchronism with second clock signals outputted from a self-excited oscillator incorporated therein, the first clock signals being asynchronous with the second clock signals, the apparatus further comprising: means for sending an access request from the data processor to the memory, the access request including address signals; means for performing an internal operation in the memory in accordance with the access request in synchronism with the second clock signals; means for sending the second clock signals from the memory to the data processor; means for transferring data from the memory to the data processor in synchronism with the second clock signals; means for writing the transferred data in the buffer memory of the data processor in synchronism with the second clock signals; and, means for outputting the data from the buffer memory to the arithmetic circuit in the data processor in synchronism with the first clock signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |