Patent US5673233A successfully refreshed from Google Patents.
US5673233A
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Synchronous memory allowing early read command in write to read transitions
Assignee: Round Rock Research LLC
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Filing: 1996-11-08
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Granted: 1997-09-30
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Expires: 2016-11-08
Abstract
Abstract A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.
Inventors
- 👤 Jeffrey P. Wright
- 👤 Hua Zheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
156 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a memory array having storage cells; a mode register for storing mode information; and a command decoder/controller responsive to selected command signals and the mode information to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 2
Dependent Claim
156 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a memory array having storage cells; a mode register for storing mode information; and a command decoder/controller responsive to selected command signals and the mode information to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 3
Dependent Claim
46 words
The memory device of claim 1 wherein the mode information includes a read latency number, wherein when the read latency number is at least three clock cycles, the command controller is allowed to initiate the read command at the second active edge of the system clock.
Claim 4
Dependent Claim
46 words
The memory device of claim 2 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory device during the second system clock cycle is the last data set transferred during the burst write operation.
Claim 5
Dependent Claim
36 words
The memory device of claim 2 wherein when the read latency number is one or two clock cycles, the command controller is not allowed to initiate the read command until after the second system clock cycle.
Claim 6
Dependent Claim
12 words
The memory device of claim 1 wherein the mode register is programmable.
Claim 7
Dependent Claim
17 words
The memory device of claim 1 wherein the memory device is a synchronous dynamic random access memory.
Claim 8
Dependent Claim
17 words
The memory device of claim 1 wherein the memory device is a synchronous graphic random access memory.
Claim 9
Dependent Claim
175 words
A memory integrated circuit responsive to command signals and operating in synchronization with active edges of a system clock, the memory integrated circuit comprising: a memory array having storage cells; a storage device storing a read latency number; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and responsive to selected command signals and the read latency number being at least a selected number of clock cycles to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory integrated circuit during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 10
Dependent Claim
175 words
A memory integrated circuit responsive to command signals and operating in synchronization with active edges of a system clock, the memory integrated circuit comprising: a memory array having storage cells; a storage device storing a read latency number; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and responsive to selected command signals and the read latency number being at least a selected number of clock cycles to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory integrated circuit during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 11
Dependent Claim
14 words
The memory integrated circuit of claim 8 wherein storage device comprises a mode register.
Claim 12
Dependent Claim
18 words
The memory integrated circuit of claim 8 wherein the selected number of clock cycles is three clock cycles.
Claim 13
Dependent Claim
48 words
The memory integrated circuit of claim 10 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory integrated circuit during the second system clock cycle is the last data set transferred during the burst write operation.
Claim 14
Dependent Claim
37 words
The memory integrated circuit of claim 10 wherein when the read latency number is one or two clock cycles, the command controller is not allowed to initiate the read command until after the second system clock cycle.
Claim 15
Dependent Claim
19 words
The memory integrated circuit of claim 8 wherein the memory integrated circuit is a synchronous dynamic random access memory.
Claim 16
Dependent Claim
19 words
The memory integrated circuit of claim 8 wherein the memory integrated circuit is a synchronous graphic random access memory.
Claim 17
Dependent Claim
200 words
A memory integrated circuit responsive to command signals and operating in synchronization with active edges of a system clock, the memory integrated circuit comprising: a memory array having storage cells; a storage device storing a read latency number; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and responsive to selected command signals and the read latency number being at least three clock cycles to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, and responsive to selected command signals and the read latency number being one or two clock cycles to initiate the read command after the second system clock cycle, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory integrated circuit during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 18
Dependent Claim
200 words
A memory integrated circuit responsive to command signals and operating in synchronization with active edges of a system clock, the memory integrated circuit comprising: a memory array having storage cells; a storage device storing a read latency number; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and responsive to selected command signals and the read latency number being at least three clock cycles to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, and responsive to selected command signals and the read latency number being one or two clock cycles to initiate the read command after the second system clock cycle, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory integrated circuit during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 19
Dependent Claim
48 words
The memory integrated circuit of claim 15 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory integrated circuit during the second system clock cycle is the last data set transferred during the burst write operation.
Claim 20
Independent Claim
184 words
A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least a selected number of clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 21
Independent Claim
184 words
A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least a selected number of clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 22
Dependent Claim
16 words
The method of claim 17 wherein the selected number of clock cycles is three clock cycles.
Claim 23
Dependent Claim
45 words
The method of claim 18 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory device during the second system clock cycle is the last data set transferred during the burst write operation.
Claim 24
Dependent Claim
34 words
The method of claim 18 wherein the step of initiating the read command is not performed until after the second system clock cycle when the read latency number is one or two clock cycles.
Claim 25
Independent Claim
209 words
A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least three clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, and initiating the read command after the second system clock cycle in response to selected command signals and the read latency number being one or two clock cycles, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 26
Independent Claim
209 words
A method of initiating a read command in a memory device responsive to command signals and mode information including a read latency number and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals and the read latency number being at least three clock cycles, a read command controlling a read operation to transfer at least one output data set from the memory device, and initiating the read command after the second system clock cycle in response to selected command signals and the read latency number being one or two clock cycles, wherein one of the multiple input data sets transferred during the burst write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 27
Dependent Claim
45 words
The method of claim 21 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory device during the second system clock cycle is the last data set transferred during the burst write operation.
References Cited (Backward Citations)
US5600605A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |