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US5672990A
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Edge-trigger pulse generator
Assignee: United Microelectronics Corp
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Filing: 1996-01-26
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Granted: 1997-09-30
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Expires: 2016-01-26
Abstract
Abstract An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment. Both of the embodiments can output a pulse having a width that is wider than a predetermined pulse width to prevent malfunction of a system utilizing the edge-trigger pulse generator as a signal generator.
Inventors
- 👤 Shyh-Liang Chaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:38
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
114 words
An edge-trigger pulse generator comprising: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate having a first input for receiving an output pulse from the first time-delay circuit and a second input for receiving an output pulse from the second time-delay circuit and providing a logical NAND output; and an inverter for receiving and inverting the output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width.
Claim 2
Dependent Claim
114 words
An edge-trigger pulse generator comprising: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate having a first input for receiving an output pulse from the first time-delay circuit and a second input for receiving an output pulse from the second time-delay circuit and providing a logical NAND output; and an inverter for receiving and inverting the output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width.
Claim 3
Dependent Claim
36 words
An edge-trigger pulse generator as claimed in claim 1 wherein the first time-delay circuit includes an odd number of inverters, and a plurality of capacitors, each capacitor connecting a point between two neighboring inverters to ground.
Claim 4
Dependent Claim
29 words
An edge-trigger pulse generator as claimed in claim 1 wherein the second time-delay circuit includes a plurality of inverters, at least one NOR gate and at least one capacitor.
Claim 5
Dependent Claim
77 words
An edge-trigger pulse generator as claimed in claim 3 wherein the second time-delay circuit includes a first inverter, a second inverter and at least one set of an inverter and NOR gate serially connected to the first inverter and the second inverter, each set of said inverter and NOR gate having a point between the inverter and the NOR gate connecting a capacitor to ground, one input terminal of each NOR gate connecting to said input pulse.
Claim 6
Dependent Claim
74 words
An edge-trigger pulse generator comprising: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; and a NOR gate having a first input for-receiving an output pulse from the first time-delay circuit and a second input for receiving an output pulse from the second time-delay circuit and providing a logical NOR output serving as the output of the edge-trigger pulse generator.
Claim 7
Dependent Claim
74 words
An edge-trigger pulse generator comprising: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; and a NOR gate having a first input for-receiving an output pulse from the first time-delay circuit and a second input for receiving an output pulse from the second time-delay circuit and providing a logical NOR output serving as the output of the edge-trigger pulse generator.
Claim 8
Dependent Claim
36 words
An edge-trigger pulse generator as claimed in claim 5 wherein the first time-delay circuit includes an odd number of inverters, and a plurality of capacitors, each capacitor connecting a point between two neighboring inverters to ground.
Claim 9
Dependent Claim
29 words
An edge-trigger pulse generator as claimed in claim 5 wherein the second time-delay circuit includes a plurality of inverters, at least one NAND gate and at least one capacitor.
Claim 10
Dependent Claim
67 words
An edge-trigger pulse generator as claimed in claim 7 wherein the second time-delay circuit includes a first inverter, a second inverter and at least one set of an inverter and NAND gate serially connected to the first inverter and the second inverter, each set of inverter and NAND gate having a node between the inverter and the NAND gate connected to a capacitor having a grounded terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-29 | 2001-03-31 | 2001-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-29 | 2005-03-31 | 2005-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-29 | 2009-03-31 | 2009-09-30 | $7700.00 | Window Closed / Lapsed |