Method for reducing silicided poly gate resistance for very small transistors

Claim 1

A method of fabricating an integrated circuit device comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode; implanting first ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask; depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; anisotropically etching said dielectric layer to leave first spacers on the sidewalls of said gate electrode; isotropically etching back said first spacers to leave second spacers extending approximately halfway up on the sidewalls of said gate electrode; implanting second ions to form heavily doped source and drain regions within said semiconductor substrate using said gate electrode and said second spacers as a mask; conformally depositing a layer of titanium over the surfaces of said semiconductor substrate; first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said second spacers; stripping said titanium layer overlying said second spacers to leave said titanium silicide layer only on the top surface and the sidewalls of said gate electrode not covered by said second spacers and on the top surface of said semiconductor substrate overlying said source and drain regions; second annealing said semiconductor substrate whereby said titanium silicide layer is transformed into a lower resistance phase; depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and providing metallization with electrical connections to complete the fabrication of said integrated circuit device.

Claim 2

A method of fabricating an integrated circuit device comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode; implanting first ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask; depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; anisotropically etching said dielectric layer to leave first spacers on the sidewalls of said gate electrode; isotropically etching back said first spacers to leave second spacers extending approximately halfway up on the sidewalls of said gate electrode; implanting second ions to form heavily doped source and drain regions within said semiconductor substrate using said gate electrode and said second spacers as a mask; conformally depositing a layer of titanium over the surfaces of said semiconductor substrate; first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said second spacers; stripping said titanium layer overlying said second spacers to leave said titanium silicide layer only on the top surface and the sidewalls of said gate electrode not covered by said second spacers and on the top surface of said semiconductor substrate overlying said source and drain regions; second annealing said semiconductor substrate whereby said titanium silicide layer is transformed into a lower resistance phase; depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and providing metallization with electrical connections to complete the fabrication of said integrated circuit device.

Claim 12

A method of forming a silicided polysilicon gate having reduced resistance in the fabrication of an integrated circuit device compared to a conventional integrated circuit device having only the top surface of a gate electrode silicided comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode; implanting first ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask; depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; anisotropically etching said dielectric layer to leave first spacers on the sidewalls of said gate electrode; isotropically etching back said first spacers to leave second spacers extending approximately halfway up on the sidewalls of said gate electrode; implanting second ions to form heavily doped source and drain regions within said semiconductor substrate using said gate electrode and said second spacers as a mask; conformally depositing a layer of titanium over the surfaces of said semiconductor substrate; first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said second spacers; stripping said titanium layer overlying said second spacers to leave said titanium silicide layer only on the top surface and the sidewalls of said gate electrode not covered by said second spacers and on the top surface of said semiconductor substrate overlying said source and drain regions wherein the effective conduction area of said titanium silicide layer on said top surface and said sidewalls of said gate electrode is greater than the conduction area of said conventional integrated circuit device having only said top surface of said gate electrode silicided; second annealing said semiconductor substrate whereby said titanium silicide layer is transformed into a lower resistance phase and wherein said lower resistance phase and said greater effective conduction area together reduce the resistance of said integrated circuit device compared to said conventional integrated circuit device; depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and providing metallization with electrical connections to complete the formation of said silicided polysilicon gate having reduced resistance in the fabrication of an integrated circuit device compared to said conventional integrated circuit device.

Claim 13

A method of forming a silicided polysilicon gate having reduced resistance in the fabrication of an integrated circuit device compared to a conventional integrated circuit device having only the top surface of a gate electrode silicided comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode; implanting first ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask; depositing a dielectric layer overlying said semiconductor substrate and said gate electrode; anisotropically etching said dielectric layer to leave first spacers on the sidewalls of said gate electrode; isotropically etching back said first spacers to leave second spacers extending approximately halfway up on the sidewalls of said gate electrode; implanting second ions to form heavily doped source and drain regions within said semiconductor substrate using said gate electrode and said second spacers as a mask; conformally depositing a layer of titanium over the surfaces of said semiconductor substrate; first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said second spacers; stripping said titanium layer overlying said second spacers to leave said titanium silicide layer only on the top surface and the sidewalls of said gate electrode not covered by said second spacers and on the top surface of said semiconductor substrate overlying said source and drain regions wherein the effective conduction area of said titanium silicide layer on said top surface and said sidewalls of said gate electrode is greater than the conduction area of said conventional integrated circuit device having only said top surface of said gate electrode silicided; second annealing said semiconductor substrate whereby said titanium silicide layer is transformed into a lower resistance phase and wherein said lower resistance phase and said greater effective conduction area together reduce the resistance of said integrated circuit device compared to said conventional integrated circuit device; depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode; and providing metallization with electrical connections to complete the formation of said silicided polysilicon gate having reduced resistance in the fabrication of an integrated circuit device compared to said conventional integrated circuit device.