US5671434A
Expired / Lapsed
US
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Microprocessor controlled apparatus
Assignee: Nokia Oyj
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Filing: 1995-06-07
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Granted: 1997-09-23
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Expires: 2015-06-07
Abstract
Abstract A microprocessor controlled apparatus includes a microprocessor (2) with e.g. eight address lines (A, 0 ,A 1 . . . A 7 ) on which signals may be applied by the microprocessor for selectively addressing a peripheral device coupled thereto, and a data device such as a LCD module (1) having data lines to which data signals may be applied for transfer into the data device. Four of the data lines (D 0 ,D 1 ,D 2 ,D 3 ) are coupled to a sub-set of the microprocessor address lines (A 2 ,A 3 ,A 4 ,A 5 ) excluding the two address lines (A 0 ,A 1 ) associated with the least significant bits. The signals on the sub-set of address lines are thus applied as data signals to the data device. When data is to be transmitted to the data device the microprocessor (2) is caused to execute a sub-routine comprising instructions having addresses such that the signal appearing on the sub-set of address lines remains substantially stable over an extended period of time allowing data to be clocked into the device even when the write timing of the microprocessor is too fast for the device to accept data directly from the data output lines of the microprocessor.
Inventors
- 👤 Andrew Menadue
- 👤 Ian Withycombe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
108 words
A microprocessor controlled apparatus for providing signals to a device comprising: a microprocessor having a plurality of dedicated address lines to which only address signals are applied during an instruction cycle, the microprocessor comprising means for maintaining all of the address signals on a sub-set of the address lines substantially constant between consecutive microprocessor instruction cycles; and a device for receiving signals on a plurality of data lines, the data lines being coupled to the sub-set of the microprocessor address lines for receiving data on the data lines from the sub-set of address lines during a device write operation that extends over a plurality of microprocessor instruction cycles.
Claim 2
Dependent Claim
108 words
A microprocessor controlled apparatus for providing signals to a device comprising: a microprocessor having a plurality of dedicated address lines to which only address signals are applied during an instruction cycle, the microprocessor comprising means for maintaining all of the address signals on a sub-set of the address lines substantially constant between consecutive microprocessor instruction cycles; and a device for receiving signals on a plurality of data lines, the data lines being coupled to the sub-set of the microprocessor address lines for receiving data on the data lines from the sub-set of address lines during a device write operation that extends over a plurality of microprocessor instruction cycles.
Claim 3
Dependent Claim
39 words
A microprocessor controlled apparatus as claimed in claim 1, wherein the microprocessor is adapted to maintain a substantially stable signal on each of the sub-set of address lines while the signal on other of the address lines is changed.
Claim 4
Dependent Claim
42 words
A microprocessor controlled apparatus as claimed in claim 2, wherein the microprocessor is conditioned to execute a sub-routine comprising instructions having addresses such that the signal appearing on the sub-set of address lines remains substantially stable during the execution of said sub-routine.
Claim 5
Dependent Claim
19 words
A microprocessor controlled apparatus as claimed in claim 3, wherein the sub-routine comprises at least one "no operation" instruction.
Claim 6
Dependent Claim
17 words
A microprocessor controlled apparatus as claimed in claim 3, wherein the sub-routine comprises m "no operation" instructions.
Claim 7
Dependent Claim
70 words
A microprocessor controlled apparatus as claimed in claim 1, wherein the sub-set of address lines excludes the address lines (A 0 , . . . A x ) associated with the x least significant bits, where x is the number of digits in the binary representation of m+1, and m+1 is the number of data lines of the data device which are coupled to the sub-set of microprocessor address lines.
Claim 8
Dependent Claim
32 words
A microprocessor controlled apparatus as claimed in claim 6, wherein the sub-set of address lines excludes the address lines (A 0 ,A 1 ) associated with the two least significant bit positions.
Claim 9
Dependent Claim
52 words
A microprocessor controlled apparatus as claimed in claim 7, wherein the data device has four data lines (D 0 ,D 1 ,D 2 ,D 3 ) coupled respectively to the address lines (A 2 ,A 3 ,A 4 ,A 5 ) associated with the third to the sixth least significant bit positions.
Claim 10
Dependent Claim
31 words
A microprocessor controlled apparatus as claimed in claim 8, wherein the data device is an 8-bit device and data is applied to the four data lines sequentially in two 4-bit segments.
Claim 11
Dependent Claim
54 words
A microprocessor controlled apparatus as claimed in claim 1, wherein the data device includes a write line to which a write signal is applied from the microprocessor during the time the signals on the sub-set of address lines are held substantially stable whereby data is transferred to the data device from the data lines.
Claim 12
Dependent Claim
28 words
A microprocessor controlled apparatus as claimed in claim 1, wherein the maximum speed at which the data device can accept data is less than the microprocessor outputs data.
Claim 13
Dependent Claim
19 words
A microprocessor controlled apparatus as claimed in claim 1, wherein the data device comprises a liquid crystal display device.
Claim 14
Dependent Claim
41 words
A microprocessor controlled apparatus as claimed in claim 1 wherein the means for maintaining the signals maintains the address signals on the sub-set of address lines for a predetermined period of time sufficiently long for the device to read the signals.
Claim 15
Independent Claim
137 words
A method of transmitting data information from a first electrical device to a second electrical device comprising steps of: sending signals from the first device to the second device through a sub-set of first device dedicated address lines that convey only address information, the sub-set being less than a total number of the first device address lines; maintaining the signals constant on all of the individual sub-set lines for a predetermined period of time while signals on other address lines of the first device change, wherein the signals on the sub-set lines are held at a constant level over the predetermined period of time to permit the signals to be written into the second device; and, in the second device, interpreting the signals that are written into the device as data information, and not as address information.
Claim 16
Independent Claim
137 words
A method of transmitting data information from a first electrical device to a second electrical device comprising steps of: sending signals from the first device to the second device through a sub-set of first device dedicated address lines that convey only address information, the sub-set being less than a total number of the first device address lines; maintaining the signals constant on all of the individual sub-set lines for a predetermined period of time while signals on other address lines of the first device change, wherein the signals on the sub-set lines are held at a constant level over the predetermined period of time to permit the signals to be written into the second device; and, in the second device, interpreting the signals that are written into the device as data information, and not as address information.
Claim 17
Dependent Claim
139 words
In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising: coupling a sub-set of the signal line set to the at least one data signal line; executing, with the digital data processor, a plurality of instructions; and during the execution of the plurality of instructions, triggering the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.
Claim 18
Dependent Claim
139 words
In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising: coupling a sub-set of the signal line set to the at least one data signal line; executing, with the digital data processor, a plurality of instructions; and during the execution of the plurality of instructions, triggering the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.
Claim 19
Dependent Claim
45 words
A method as set forth in claim 15, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.
Claim 20
Dependent Claim
79 words
A method as set forth in claim 15, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.
Claim 21
Dependent Claim
30 words
A method as set forth in claim 17, wherein an instruction set is selected for execution as a function of a value of data to be input to the device.
Claim 22
Dependent Claim
41 words
A method as set forth in claim 15, wherein the device includes a terminal for inputting a write signal, and wherein the step of triggering includes a step of activating the write signal during the execution of the plurality of instructions.
Claim 23
Dependent Claim
85 words
A method as set forth in claim 15, wherein the device includes a terminal for inputting a write signal, wherein the digital data processor includes a terminal for outputting a bit serial data signal, wherein the device write signal terminal is coupled to the processor bit serial data terminal, and wherein the step of triggering includes a step of activating the write signal during the execution of the plurality of instructions by outputting a predetermined bit serial data signal from the bit serial data terminal.
Claim 24
Dependent Claim
128 words
A data processing system, comprising: a memory comprised of a plurality of addressable storage locations for storing executable instructions; a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set; wherein said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is triggered to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.
Claim 25
Dependent Claim
128 words
A data processing system, comprising: a memory comprised of a plurality of addressable storage locations for storing executable instructions; a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set; wherein said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is triggered to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.
Claim 26
Dependent Claim
47 words
A data processing system as set forth in claim 21, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.
Claim 27
Dependent Claim
81 words
A data processing system as set forth in claim 21, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.
Claim 28
Dependent Claim
101 words
A data processing system as set forth in claim 21, wherein the device includes a terminal for inputting a write signal that is activated to write data appearing on the data signal lines into the device, wherein the digital data processor includes a terminal for outputting a bit serial data signal, wherein the device write signal terminal is coupled to the processor bit serial data terminal, and wherein the digital data processor includes means for activating the write signal during the execution of the plurality of instructions by outputting a predetermined bit serial data signal from the bit serial data terminal.
Claim 29
Dependent Claim
93 words
A data processing system as set forth in claim 21, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set and have a value that ranges at least from 00 to 11.
Claim 30
Dependent Claim
21 words
A data processing system as set forth in claim 21, wherein said device is a display device for a radio telephone.
Claim 31
Dependent Claim
47 words
A data processing system as set forth in claim 26, wherein the plurality of instructions are predeterminally stored in the memory such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant.
Claim 32
Dependent Claim
81 words
A data processing system as set forth in claim 26, wherein the memory stores a plurality of instruction sets each of which is comprised of a plurality of instructions, wherein individual ones of the plurality of instruction sets are aligned to a memory address boundary such that the memory address signals that appear on the sub-set of the signal line set, during the execution of the plurality of instructions, remain constant during the execution of instructions of a selected instruction set.
Claim 33
Dependent Claim
51 words
A data processing system as set forth in claim 26, wherein the device includes a terminal for inputting a write signal, and wherein the step of causing the device to input the memory address signals includes a step of activating the write signal during the execution of the plurality of instructions.
Claim 34
Dependent Claim
139 words
In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising: coupling a sub-set of the signal line set to the at least one data signal line; executing, with the digital data processor, a plurality of instructions; and during the execution of the plurality of instructions, causing the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.
Claim 35
Dependent Claim
139 words
In a data processing system having a memory comprised of a plurality of addressable storage locations for storing executable instructions, a digital data processor having a port comprised of a set of signal lines for outputting memory address signals for specifying individual ones of the addressable storage locations, and at least one device having a port comprised of at least one data signal line for inputting data, a method for inputting data to the device, comprising: coupling a sub-set of the signal line set to the at least one data signal line; executing, with the digital data processor, a plurality of instructions; and during the execution of the plurality of instructions, causing the device to input, on the at least one data signal line, the memory address signals that are output on the sub-set of the signal line set.
Claim 36
Dependent Claim
128 words
A data processing system, comprising: a memory comprised of a plurality of addressable storage locations for storing executable instructions; a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set; wherein said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is caused to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.
Claim 37
Dependent Claim
128 words
A data processing system, comprising: a memory comprised of a plurality of addressable storage locations for storing executable instructions; a digital data processor having a port comprised of a set of signal lines coupled to said memory for outputting memory address signals for specifying individual ones of the addressable storage locations; and at least one device having a port comprised of data signal lines for inputting data, said data signal lines being coupled to a sub-set of the address signal line set; wherein said digital data processor executes a plurality of instructions and, during the execution of the plurality of instructions, said device is caused to input, on said data signal lines, the memory address signals that are output on the sub-set of the address signal line set.
Claim 38
Dependent Claim
19 words
A system as set forth in claim 31, wherein said device is a display device for a radio telephone.
References Cited (Backward Citations)
US4486833A
Cited
EP0185258A2
Cited
US4713749A
Cited
US4713748A
Cited
US5125088A
Cited
GB2234093A
Cited
US5337068A
Cited
US5247636A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |