EP0185258A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor system
Assignee: Bull HN Information Systems Italia SpA
•
Filing: 1985-12-05
•
Granted: —
•
Expires: 2005-12-05
Abstract
Abstract A microprocessor system comprises a microprocessor having multiplexed address/data bus communicating with a plurality of memory and input/output devices.A demultiplexing register allows to demultiplex the microprocessor address/data bus, while a decoder allows to select, according to the most significant address bits, one of the system devices, during a microprocessor external operation.The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, an information is latched representative of the less significant address portion.A datum information transfer to an output gate TTL is obtained by having an external operation executed by the microprocessor such that the most significant address bits select such gate and the less significant address portion represents the datum to be transferred.
Inventors
- 👤 Giorgio Costantini
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 02:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
Microprocessor system comprising: - microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, - a demultiplexing register having inputs connected to said second group of multiplexed lines and outputs, - a control memory having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input. - a plurality of TTL output gates provided with data inputs and one enabling input - a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and of said output gates TTL and - direct connection between the outputs of said demultiplexing register and the data inputs of said TTL output gates.
Claim 2
Dependent Claim
182 words
Microprocessor system comprising: - microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, - a demultiplexing register having inputs connected to said second group of multiplexed lines and outputs, - a control memory having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input. - a plurality of TTL output gates provided with data inputs and one enabling input - a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and of said output gates TTL and - direct connection between the outputs of said demultiplexing register and the data inputs of said TTL output gates.
Claim 3
Dependent Claim
33 words
Microprocessor system as per claim 1 characterised by that said address register L, intended to contain an address portion, is loaded with an information to be transferred to one of said output gates.
Claim 4
Dependent Claim
250 words
In a microprocessor system comprising: - a microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, - a demultiplexing register having inputs connected to said second group of multiplexed lines and outputs, - a control memory having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input, - a plurality of TTL output gates provided with data inputs and one enabling input - a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and of said output gates TTL and - a direct connection between the output of said demultiplexing register and the data inputs of said TTL output gates the information transfer method from said microprocessor to one of said output gates TTL comprising the following steps: - loading said address register H with an information selecting an output gate, - loading said address register L with the information to be transferred, - executing a fictitious memory transfer operation to the address specified by the content of said address register H and L.
Claim 5
Dependent Claim
250 words
In a microprocessor system comprising: - a microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines, - a demultiplexing register having inputs connected to said second group of multiplexed lines and outputs, - a control memory having address inputs connected to the outputs of said demultiplexing register and to one line at least of said first group, having information outputs connected to said second group of lines, and a selection input, - a plurality of TTL output gates provided with data inputs and one enabling input - a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and of said output gates TTL and - a direct connection between the output of said demultiplexing register and the data inputs of said TTL output gates the information transfer method from said microprocessor to one of said output gates TTL comprising the following steps: - loading said address register H with an information selecting an output gate, - loading said address register L with the information to be transferred, - executing a fictitious memory transfer operation to the address specified by the content of said address register H and L.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.