Patent JPS56129374A successfully refreshed from Google Patents.
Patent US5671152A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5671152A Expired / Lapsed US ⏱️ 0.0 years remaining

Efficient generation of negative fill shapes for chips and packages

Assignee: International Business Machines Corp
•
Filing: 1995-05-19
•
Granted: 1997-09-23
•
Expires: 2015-05-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill holes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill holes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.

Inventors

  • 👤 Mark A. Lavin
  • 👤 Lars W. Liebmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 04:54
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F2119/00; G06F2119/18; Y; Y02; Y02P; Y02P90/00; Y02P90/02

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 160 words
A computer-implemented method for modifying an integrated circuit chip or package design by adding negative fill shapes to the design comprising the steps of: inputting an original design, including areas to which negative fill shapes are to be added, as a data file; deoverlapping areas to which negative fill shapes are to be added and fracturing the deoverlaped areas to which negative fill shapes are to be added into geometric shapes; determining a maximum set of unit cells, each containing one or more negative fill shapes, that fit within borders of the fractured areas to which negative fill shapes are to be added and generating areas with the negative fill shapes; subtracting the areas to which negative fill shapes are to be added from the original design; and combining the generated areas with the negative fill shapes with the original design minus the areas to which negative fill shapes are to be added to produce a resultant design for fabrication.
Claim 2
Dependent Claim 160 words
A computer-implemented method for modifying an integrated circuit chip or package design by adding negative fill shapes to the design comprising the steps of: inputting an original design, including areas to which negative fill shapes are to be added, as a data file; deoverlapping areas to which negative fill shapes are to be added and fracturing the deoverlaped areas to which negative fill shapes are to be added into geometric shapes; determining a maximum set of unit cells, each containing one or more negative fill shapes, that fit within borders of the fractured areas to which negative fill shapes are to be added and generating areas with the negative fill shapes; subtracting the areas to which negative fill shapes are to be added from the original design; and combining the generated areas with the negative fill shapes with the original design minus the areas to which negative fill shapes are to be added to produce a resultant design for fabrication.
Claim 3
Dependent Claim 30 words
The computer-implemented method for modifying an integrated circuit chip or package design recited in claim 1 wherein the negative fill shapes are geometric shapes which are rectangles, quadrilaterals and triangles.
Claim 4
Dependent Claim 55 words
The computer-implemented method for modifying an integrated circuit chip or package design recited in claim 1 further comprising the step of determining placements of the negative fill shapes unit cell by generating a repetitive array of unit cells and selecting those completely covered by the areas to which negative fill shapes are to be added.
Claim 5
Dependent Claim 72 words
The computer-implemented method for modifying an integrated circuit chip or package design recited in claim 1 further comprising the steps of: determining placements of the fill pattern unit cell by shrinking the areas to which negative fill shapes are to be added; determining which of an infinite regular array of grid points fall in the areas to which negative fill shapes are to be added; and generating a placement for each point.
Claim 6
Dependent Claim 86 words
The computer-implemented method for modifying an integrated circuit chip or package design recited in claim 1 further comprising the steps of: determining placements of the fill pattern unit cell by shrinking a rectangular area to which negative fill shapes are to be added; determining a rectangular subset of an infinite regular array of grid points that fall in the areas to which negative fill shapes are to be added; and generating a step-and-repeat placement of the negative fill shapes unit cell corresponding to that rectangular subset.
Claim 7
Dependent Claim 166 words
A programmed computer system for modifying an integrated circuit chip or package design represented by a data file, comprising: means for accessing said data file of an original design, including areas to which negative fill shapes are to be added, as a data file, and deoverlapping areas to which negative fill shapes are to be added and fracturing the deoverlaped areas to which negative fill shapes are to be added into geometric shapes; computing means for determining a maximum set of unit cells, each containing one or more negative fill shapes, that fit within borders of the fractured areas to which negative fill shapes are to be added and generating areas containing negative fill shapes, said computing means subtracting the areas to which negative fill shapes are to be added from the original design; and combining means for combining the areas containing negative fill shapes with the original design minus the areas to which negative fill shapes are to be added to generate a resultant design.
Claim 8
Dependent Claim 166 words
A programmed computer system for modifying an integrated circuit chip or package design represented by a data file, comprising: means for accessing said data file of an original design, including areas to which negative fill shapes are to be added, as a data file, and deoverlapping areas to which negative fill shapes are to be added and fracturing the deoverlaped areas to which negative fill shapes are to be added into geometric shapes; computing means for determining a maximum set of unit cells, each containing one or more negative fill shapes, that fit within borders of the fractured areas to which negative fill shapes are to be added and generating areas containing negative fill shapes, said computing means subtracting the areas to which negative fill shapes are to be added from the original design; and combining means for combining the areas containing negative fill shapes with the original design minus the areas to which negative fill shapes are to be added to generate a resultant design.

References Cited (Backward Citations)

US4975854A Cited
JPH03129821A Cited
US5251140A Cited
US5278105A Cited
US5416722A Cited
US5459093A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-22 2001-03-24 2001-09-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-22 2005-03-24 2005-09-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-22 2009-03-24 2009-09-23 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag