Patent US5670404A successfully refreshed from Google Patents.
US5670404A
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US
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Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer
Assignee: Industrial Technology Research Institute
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Filing: 1996-06-21
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Granted: 1997-09-23
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Expires: 2016-06-21
Abstract
Abstract An improved method for fabricating self-aligned contacts in a planar insulating layer to the source/drain contact areas on field effect transistors (FETs), formed in part from a first polycide layer, is achieved using an undoped polysilicon layer as an etch-stop layer. The planar insulating layer provides a good surface for patterning a second polycide layer without intralevel shorts that would otherwise occur over a rough topography. This is of particular use for forming the array of bit lines over the array of word lines for DRAM circuits. The method involves providing a patterned undoped polysilicon layer on the gate electrodes. A planarized insulating layer, such as reflowed borophosphosilicate glass (BPSG) is then deposited and reflowed to fill the high aspect ratio recesses between the closely spaced word lines. The bit line contact openings are anisotropically plasma etched in the BPSG to the FET source/drain contact areas, while using the undoped polysilicon layer over the gate electrodes as an etch-stop layer to form self-aligned contacts without etching into the gate electrodes.
Inventors
- 👤 Chang-Ming Dai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:10
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10W; H10W20/00; H10W20/01; H10W20/031
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
327 words
A method for fabricating self-aligned bit line contacts on a dynamic random access memory device comprising the steps of: providing a semiconductor substrate having device areas surrounded by field oxide areas; forming a gate oxide on said device areas; depositing a first polycide layer on said gate oxide and elsewhere on said field oxide areas; depositing a first insulating layer over said first polycide layer; depositing an etch-stop layer on said first insulating layer; patterning said etch-stop layer, said first insulating layer, and said first polycide layer thereby forming an array of word lines, said word lines extending over said gate oxide forming field effect transistor gate electrodes; removing portions of said etch-stop layer while leaving portions over said word lines adjacent to areas where bit line contact openings are desired; forming lightly doped source/drain areas by ion implantation; depositing a conformal second insulating layer and anisotropically plasma etching back said second insulating layer thereby forming sidewall spacers on said array of word lines; depositing a conformal third insulating layer over said array of word lines; depositing a fourth insulating layer over said third insulating layer; planarizing said fourth insulating layer and filling recesses between said word lines; coating a photoresist layer on said planar fourth insulating layer and providing openings over said desired bit line contact openings and further extending over said etch-stop layer on said word lines; etching said bit line contact openings in said fourth and third insulating layers to said etch-stop layer, and continuing said etching of said fourth and third insulating layers between portions of said etch-stop layer to the surface of said device areas, thereby forming said self-aligned bit line contact openings; depositing a conformal second polycide layer in said bit line contact openings and elsewhere over said planar fourth insulating layer; patterning said second polycide and forming an array of polycide bit lines essentially orthogonal to said word lines, thereby completing said self-aligned bit line contacts and said bit lines.
Claim 2
Independent Claim
327 words
A method for fabricating self-aligned bit line contacts on a dynamic random access memory device comprising the steps of: providing a semiconductor substrate having device areas surrounded by field oxide areas; forming a gate oxide on said device areas; depositing a first polycide layer on said gate oxide and elsewhere on said field oxide areas; depositing a first insulating layer over said first polycide layer; depositing an etch-stop layer on said first insulating layer; patterning said etch-stop layer, said first insulating layer, and said first polycide layer thereby forming an array of word lines, said word lines extending over said gate oxide forming field effect transistor gate electrodes; removing portions of said etch-stop layer while leaving portions over said word lines adjacent to areas where bit line contact openings are desired; forming lightly doped source/drain areas by ion implantation; depositing a conformal second insulating layer and anisotropically plasma etching back said second insulating layer thereby forming sidewall spacers on said array of word lines; depositing a conformal third insulating layer over said array of word lines; depositing a fourth insulating layer over said third insulating layer; planarizing said fourth insulating layer and filling recesses between said word lines; coating a photoresist layer on said planar fourth insulating layer and providing openings over said desired bit line contact openings and further extending over said etch-stop layer on said word lines; etching said bit line contact openings in said fourth and third insulating layers to said etch-stop layer, and continuing said etching of said fourth and third insulating layers between portions of said etch-stop layer to the surface of said device areas, thereby forming said self-aligned bit line contact openings; depositing a conformal second polycide layer in said bit line contact openings and elsewhere over said planar fourth insulating layer; patterning said second polycide and forming an array of polycide bit lines essentially orthogonal to said word lines, thereby completing said self-aligned bit line contacts and said bit lines.
Claim 3
Dependent Claim
22 words
The method of claim 1, wherein a polysilicon film in said first polycide layer is deposited in-situ doped with an N-type dopant.
Claim 4
Dependent Claim
18 words
The method of claim 1, wherein said first polycide layer thickness is between about 1000 and 3000 Angstroms.
Claim 5
Dependent Claim
30 words
The method of claim 1, wherein said first insulating layer is a chemical vapor deposited silicon oxide (SiO 2 ) having a thickness of between about 1000 and 3000 Angstroms.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein said etch-stop layer is an undoped polysilicon layer.
Claim 7
Dependent Claim
18 words
The method of claim 5, wherein said undoped polysilicon layer is between about 500 and 1500 Angstroms thick.
Claim 8
Dependent Claim
23 words
The method of claim 1, wherein said conformal third insulating layer is deposited to a thickness of between about 400 and 1500 Angstroms.
Claim 9
Dependent Claim
25 words
The method of claim 1, wherein said fourth insulating layer is a borophosphosilicate glass (BPSG) having a thickness of between about 2000 and 5000 Angstroms.
Claim 10
Dependent Claim
33 words
The method of claim 8, wherein said BPSG is locally planarized by annealing at a temperature of between about 800° and 900° C. for a time of between about 10 and 60 minutes.
Claim 11
Dependent Claim
32 words
The method of claim 1, wherein said bit line contact openings are formed by anisotropic plasma etching in a gas mixture of CF 4 , H 2 , and CHF 3 .
Claim 12
Dependent Claim
25 words
The method of claim 10, wherein said anisotropic, plasma etching has an etch-rate ratio of BPSG-etch-rate to undoped polysilicon-etch-rate of between about 15:1 and 100:1.
Claim 13
Dependent Claim
20 words
The method of claim 1, wherein said second polycide layer has a thickness of between about 1000 and 3000 Angstroms.
Claim 14
Independent Claim
337 words
A method for fabricating self-aligned bit line contacts on a dynamic random access memory device comprising the steps of: providing a semiconductor substrate having device areas surrounded by field oxide areas; forming a gate oxide on said device areas; depositing a first polycide layer on said gate oxide and elsewhere on said field oxide areas; depositing a first insulating layer over said first polycide layer; depositing an etch-stop layer on said first insulating layer, wherein said etch-stop layer is an undoped polysilicon layer; patterning said etch-stop layer, said first insulating layer, and said first polycide layer thereby forming an array of word lines, said word lines extending over said gate oxide forming field effect transistor gate electrodes; removing portions of said etch-stop layer while leaving portions over said word lines adjacent to areas where bit line contact openings are desired; forming lightly doped source/drain areas by ion implantation; depositing a conformal second insulating layer and anisotropically plasma etching back said second insulating layer thereby forming sidewall spacers on said array of word lines; depositing a conformal third insulating layer over said array of word lines; depositing a fourth insulating layer over said third insulating layer; planarizing said fourth insulating layer and filling recesses between said word lines; coating a photoresist layer on said planar fourth insulating layer and providing openings over said desired bit line contact openings and further extending over said etch-stop layer on said word lines; etching said bit line contact openings in said fourth and third insulating layers to said etch-stop layer, and continuing said etching of said fourth and third insulating layers between portions of said etch-stop layer to the surface of said device areas, thereby forming said self-aligned bit line contact openings; depositing a conformal second polycide layer in said bit line contact openings and elsewhere over said planar fourth insulating layer; patterning said second polycide layer and forming an array of polycide bit lines essentially orthogonal to said word lines, thereby completing said self-aligned bit line contacts and said bit lines.
Claim 15
Independent Claim
337 words
A method for fabricating self-aligned bit line contacts on a dynamic random access memory device comprising the steps of: providing a semiconductor substrate having device areas surrounded by field oxide areas; forming a gate oxide on said device areas; depositing a first polycide layer on said gate oxide and elsewhere on said field oxide areas; depositing a first insulating layer over said first polycide layer; depositing an etch-stop layer on said first insulating layer, wherein said etch-stop layer is an undoped polysilicon layer; patterning said etch-stop layer, said first insulating layer, and said first polycide layer thereby forming an array of word lines, said word lines extending over said gate oxide forming field effect transistor gate electrodes; removing portions of said etch-stop layer while leaving portions over said word lines adjacent to areas where bit line contact openings are desired; forming lightly doped source/drain areas by ion implantation; depositing a conformal second insulating layer and anisotropically plasma etching back said second insulating layer thereby forming sidewall spacers on said array of word lines; depositing a conformal third insulating layer over said array of word lines; depositing a fourth insulating layer over said third insulating layer; planarizing said fourth insulating layer and filling recesses between said word lines; coating a photoresist layer on said planar fourth insulating layer and providing openings over said desired bit line contact openings and further extending over said etch-stop layer on said word lines; etching said bit line contact openings in said fourth and third insulating layers to said etch-stop layer, and continuing said etching of said fourth and third insulating layers between portions of said etch-stop layer to the surface of said device areas, thereby forming said self-aligned bit line contact openings; depositing a conformal second polycide layer in said bit line contact openings and elsewhere over said planar fourth insulating layer; patterning said second polycide layer and forming an array of polycide bit lines essentially orthogonal to said word lines, thereby completing said self-aligned bit line contacts and said bit lines.
Claim 16
Dependent Claim
22 words
The method of claim 13, wherein a polysilicon film of said first polycide layer is deposited in-situ doped with an N-type dopant.
Claim 17
Dependent Claim
47 words
The method of claim 13, wherein said first polycide layer thickness is between about 1000 and 3000 Angstroms having a polysilicon film with a thickness of between about 500 and 1500 Angstroms and a tungsten silicide layer with a thickness of between about 500 and 1500 Angstroms.
Claim 18
Dependent Claim
30 words
The method of claim 13, wherein said first insulating layer is a chemical vapor deposited silicon oxide (SiO 2 ) having a thickness of between about 1000 and 3000 Angstroms.
Claim 19
Dependent Claim
18 words
The method of claim 13, wherein said undoped polysilicon layer is between about 500 and 1500 Angstroms thick.
Claim 20
Dependent Claim
23 words
The method of claim 13, wherein said conformal third insulating layer is deposited to a thickness of between about 400 and 1500 Angstroms.
Claim 21
Dependent Claim
25 words
The method of claim 13, wherein said fourth insulating layer is a borophosphosilicate glass (BPSG) having a thickness of between about 2000 and 5000 Angstroms.
Claim 22
Dependent Claim
33 words
The method of claim 19, wherein said BPSG is locally planarized by annealing at a temperature of between about 800° and 900° C. for a time of between about 10 and 60 minutes.
Claim 23
Dependent Claim
32 words
The method of claim 13, wherein said bit line contact openings are formed by anisotropic plasma etching in a gas mixture of CF 4 , H 2 , and CHF 3 .
Claim 24
Dependent Claim
25 words
The method of claim 21, wherein said anisotropic plasma etching has an etch-rate ratio of BPSG-etch-rate to undoped polysilicon-etch-rate of between about 15:1 and 100:1.
Claim 25
Dependent Claim
47 words
The method of claim 13, wherein said second polycide layer thickness is between about 1000 and 3000 Angstroms having a polysilicon film with a thickness of between about 500 and 1500 Angstroms and a tungsten silicide layer with a thickness of between about 500 and 1500 Angstroms.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |