System and method for using a half-clock module to implement computer timing control circuitry

Claim 2

A half-clock timing control module comprising: clock signal input means for receiving a system clock signal; control signal input means for receiving module control signals; module means responsive to the clock signal and the module control signals for generating a module output signal which changes state on selected rising and falling edges of the system clock signal; and module signal output means for providing the module output signal.

Claim 3

The module of claim 1 wherein the module control signals comprise a toggle-rising signal and a toggle-falling signal.

Claim 4

The module of claim 2 wherein the module control signals are sampled on rising edges of the system clock signal.

Claim 5

The module of claim 3, and further comprising a computer DRAM controller which provides the module control signals.

Claim 6

The module of claim 4, further comprising a DRAM circuit and wherein the module output signal is provided to the DRAM circuit.

Claim 7

A timing control device comprising: a system clock signal input for receiving a system clock signal having alternating rising edges and falling edges; toggle-control signal inputs for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal which have an asserted state and a deasserted state; and a half-clock module for generating a module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.

Claim 8

A timing control device comprising: a system clock signal input for receiving a system clock signal having alternating rising edges and falling edges; toggle-control signal inputs for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal which have an asserted state and a deasserted state; and a half-clock module for generating a module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.

Claim 9

The device of claim 6, and further comprising a computer DRAM controller which provides the toggle-rising signal and the toggle-falling signal.

Claim 10

The device of claim 7, and further comprising a DRAM circuit and wherein the DRAM circuit receives the module output signal.

Claim 11

The device of claim 6 wherein the half-clock module comprises: a toggle-falling T flip-flop for receiving the system clock signal and the toggle-falling signal, and responsively generating a toggle-falling T flip-flop output signal; a delay D flip-flop for receiving the system clock signal and the toggle-falling T flip-flop output signal, and responsively generating a delay D flip-flop output signal, said D flip-flop having an inverting clock input for receiving said clock signal; a toggle-rising T flip-flop for receiving the system clock signal and the toggle-rising signal, and responsively generating a toggle-rising T flip-flop output signal; and an output XOR gate for receiving the delay D flip-flop output signal and the toggle-rising T flip-flop output signal and responsively generating the module output signal.

Claim 12

The device of claim 6, further comprising a microprocessor which provides the toggle-rising signal and the toggle-falling signal.

Claim 13

The device of claim 6, further comprising a pulse module input circuit responsive to a pulse-rising signal and to a pulse-falling signal to provide the toggle-rising signals and the toggle-falling signals which control the half-clock module, to generate a half-clock pulse synchronized with a system clock signal edge selected by the pulse-rising signal and the pulse-falling signal.

Claim 14

The device of claim 6, further comprising a set/reset module input circuit responsive to a set-rising signal, a set-falling signal, a reset-rising signal, and a reset-falling signal, to provide the toggle-rising signals and the toggle-falling signals which control the half-clock module, to set or reset the half-clock module output signal on a selected one of the edges of the system clock signal.

Claim 15

The device of claim 6, further comprising a data module input circuit responsive to a sample-rising signal and a sample-falling signal to provide toggle-rising signals and toggle-falling signals to control the half-clock module which propagates a data value input signal as the half-clock module output signal on a system clock signal edge selected by the sample-rising signal and the sample-falling signal.

Claim 18

The method of claim 14, and further comprising the step of using a computer DRAM controller to generate the toggle-rising signal and the toggle-falling signal.

Claim 19

The method of claim 15, further comprising the step of providing a DRAM circuit and wherein the DRAM circuit receives the module output signal.

Claim 20

Half-clock design module means comprising: means for receiving a system clock signal having alternating rising edges and falling edges; means for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal; means for sampling the toggle-control signals on the rising edges of the system clock signal; and means for generating a half-clock module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.

Claim 21

Half-clock design module means comprising: means for receiving a system clock signal having alternating rising edges and falling edges; means for receiving toggle-control signals including a toggle-rising signal and a toggle-falling signal; means for sampling the toggle-control signals on the rising edges of the system clock signal; and means for generating a half-clock module output signal by, on each rising edge of the system clock signal, sampling the toggle-rising signal and the toggle-falling signal, and when the sampled toggle-rising signal is asserted, toggling the module output signal, and when the sampled toggle-falling signal is asserted, toggling the module output signal on the next falling edge of the system clock signal.

Claim 22

The module of claim 17, and further comprising a computer DRAM controller which provides the toggle-rising signal and the toggle-falling signal.

Claim 23

The module of claim 17 and further comprising a microprocessor which provides the toggle-rising and toggle-falling signal.

Claim 24

The module of claim 18, further comprising a DRAM circuit and wherein the DRAM circuit receives the module output signal.