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US5668043A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming isolated regions in a semiconductor device

Assignee: SK Hynix Inc
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Filing: 1996-02-22
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Granted: 1997-09-16
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Expires: 2016-02-22
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Abstract

Abstract The present invention provides a method for forming a field oxide layer without the use of the LOCOS process. Accordingly, the present invention provides a superior effect capable of increasing the active region and improving the integration of semiconductor devices, preventing the bird's beak from being generated. Also, in the present invention, since the width of the field oxide layer is the same as that of a spacer on the sidewall of the insulating layer, the area of the field oxide layer is minimized.

Inventors

  • 👤 Sang Hoon Park

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 12:08
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P52/00; H10P52/40; H10P52/403; H10W10/014; H10W10/0148; H10W10/018; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 174 words
A method for isolating a semiconductor device, comprising the steps of: forming a first insulating layer exposing a field region of a substrate; forming a transition metal spacer on said substrate and on the sidewall of said first insulating layer; forming a second insulating layer on the entire resultant structure; diffusing ions of said transition metal spacer into said substrate by thermally treating said substrate; polishing said second insulating layer until said transition metal spacer is exposed, a portion thereof remaining not to be removed; forming a trench in said substrate by removing said transition metal spacer and ion-diffused substrate under said transition metal spacer; forming a third insulating layer on the entire resultant structure, filling up the said trench; forming a photoresist pattern on said third insulating layer and on said field region; etching said third insulating layer using said photoresist pattern as an etching barrier; exposing a portion of said substrate by removing said. photoresist pattern and said first insulating layer; and forming epitaxial layers on said exposed substrate as active regions.
Claim 2
Independent Claim 174 words
A method for isolating a semiconductor device, comprising the steps of: forming a first insulating layer exposing a field region of a substrate; forming a transition metal spacer on said substrate and on the sidewall of said first insulating layer; forming a second insulating layer on the entire resultant structure; diffusing ions of said transition metal spacer into said substrate by thermally treating said substrate; polishing said second insulating layer until said transition metal spacer is exposed, a portion thereof remaining not to be removed; forming a trench in said substrate by removing said transition metal spacer and ion-diffused substrate under said transition metal spacer; forming a third insulating layer on the entire resultant structure, filling up the said trench; forming a photoresist pattern on said third insulating layer and on said field region; etching said third insulating layer using said photoresist pattern as an etching barrier; exposing a portion of said substrate by removing said. photoresist pattern and said first insulating layer; and forming epitaxial layers on said exposed substrate as active regions.
Claim 3
Dependent Claim 29 words
A method in accordance with claim 1, wherein the step of forming a trench in said substrate further comprises the step of implanting channel stop ions into said trench.
Claim 4
Dependent Claim 23 words
A method in accordance with claim 1, wherein said first insulating layer is made of a pad oxide layer and a nitride layer.
Claim 5
Dependent Claim 14 words
A method in accordance with claim 1, wherein said substrate is a silicon substrate.
Claim 6
Dependent Claim 27 words
A method in accordance with claim 4, wherein said ions diffused into said substrate from said transition metal spacer forms a silicide layer in said silicon substrate.
Claim 7
Dependent Claim 16 words
A method in accordance with claim 1, wherein said second insulating layer is a nitride layer.
Claim 8
Dependent Claim 17 words
A method in accordance with claim 1, wherein said third insulating layer is a tetraethoxysilane (TEOS) layer.
Claim 9
Dependent Claim 20 words
A method in accordance with claim 1, wherein said transition metal is one of W, Ti, Ta, Mo or Nb.
Claim 10
Independent Claim 176 words
A method for isolating a semiconductor device, comprising the steps of: forming a first insulating layer exposing a portion of a substrate; forming a transition metal spacer on said substrate and on the sidewall of said first insulating layer; forming a second insulating layer on the entire resultant structure; diffusing ions of said transition metal spacer into said substrate by thermally treating said substrate; polishing said second insulating layer such that said transition metal spacer is exposed, a portion thereof remaining not to be removed; forming a trench in said substrate by removing said transition metal spacer and ion-diffused substrate under said transition metal spacer; forming a third insulating layer on the entire resultant structure, filling up the said trench; polishing the stacked layers until said transition metal spacer is overall exposed, performing the planarization process; exposing a portion of said substrate by removing said second insulating layer and said first insulating layer, which remain not to be removed, such that said substrate is exposed; and forming epitaxial layers on said exposed substrate as active regions.
Claim 11
Independent Claim 176 words
A method for isolating a semiconductor device, comprising the steps of: forming a first insulating layer exposing a portion of a substrate; forming a transition metal spacer on said substrate and on the sidewall of said first insulating layer; forming a second insulating layer on the entire resultant structure; diffusing ions of said transition metal spacer into said substrate by thermally treating said substrate; polishing said second insulating layer such that said transition metal spacer is exposed, a portion thereof remaining not to be removed; forming a trench in said substrate by removing said transition metal spacer and ion-diffused substrate under said transition metal spacer; forming a third insulating layer on the entire resultant structure, filling up the said trench; polishing the stacked layers until said transition metal spacer is overall exposed, performing the planarization process; exposing a portion of said substrate by removing said second insulating layer and said first insulating layer, which remain not to be removed, such that said substrate is exposed; and forming epitaxial layers on said exposed substrate as active regions.
Claim 12
Dependent Claim 29 words
A method in accordance with claim 9, wherein the step of forming a trench in said substrate further comprises the step of implanting channel stop ions into said trench.
Claim 13
Dependent Claim 23 words
A method in accordance with claim 9, wherein said first insulating layer is made of a pad oxide layer and a nitride layer.
Claim 14
Dependent Claim 14 words
A method in accordance with claim 9, wherein said substrate is a silicon substrate.
Claim 15
Dependent Claim 27 words
A method in accordance with claim 12, wherein said ions diffused into said substrate from said transition metal spacer forms a silicide layer in said silicon substrate.
Claim 16
Dependent Claim 16 words
A method in accordance with claim 9, wherein said second insulating layer is a nitride layer.
Claim 17
Dependent Claim 17 words
A method in accordance with claim 9, wherein said third insulating layer is a tetraethoxysilane (TEOS) layer.
Claim 18
Dependent Claim 20 words
A method in accordance with claim 9, wherein said transition metal is one of W, Ti, Ta, Mo or Nb.

References Cited (Backward Citations)

JPS5766627A Cited
JPS5893220A Cited
JPH01321629A Cited
US5256591A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-15 2001-03-17 2001-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-15 2005-03-17 2005-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-15 2009-03-17 2009-09-16 $7700.00 Window Closed / Lapsed

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