Patent US5666559A successfully refreshed from Google Patents.
US5666559A
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Fail-safe communication abort mechanism for parallel ports with selectable NMI or parallel port interrupt
Assignee: Advanced Micro Devices Inc
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Filing: 1996-10-09
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Granted: 1997-09-09
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Expires: 2016-10-09
Abstract
Abstract A computer system is provided including a processor and a parallel port configured to transfer data to or from a peripheral device. The parallel port includes a data buffer for receiving data transferred on a system bus when the processor executes a write cycle to the parallel port. A control unit associated with the parallel port decodes the address signals of the system bus to selectively latch data within the data buffer, and generates handshake signals to the peripheral device to indicate that write data is presently contained within the data buffer. The peripheral device consequently receives the data and provides an acknowledge signal to the control unit. The control unit thereafter generates a ready signal to indicate to the processor that the data has been written into the peripheral device. A time-out counter is coupled to the control unit to determine whether the peripheral device has returned the acknowledge signal within a predetermined time-out period after the control unit asserts the handshake signal to the peripheral device indicating that data is available at the parallel port. If the time-out period expires and the peripheral device did not return an acknowledge signal, the control unit releases the processor from the current cycle by asserting the ready signal on the system bus. The control unit further asserts an error flag within a status register to indicate that a failure occurred. In response to assertion of the error flag, the control unit asserts an interrupt signal which effectively alerts the processor of a failure. The processor thereafter executes code from an interrupt service routine during which the status register may be read to determine that the failure was associated with the parallel port. The parallel port is also associated with a configuration register that controls whether a non-maskable interrupt or a parallel port interrupt is asserted in response to the assertion of the error flag.
Inventors
- 👤 Michael T. Wisor
- 👤 Scott C. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:52
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/0706; G06F11/0745; G06F11/0766; G06F11/0772; G06F11/0793
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
364 words
A computer system comprising: a processing unit; a local bus coupled to said processing unit; a peripheral bus; a peripheral bus bridge coupled to said local bus and said peripheral bus; a peripheral device; and a parallel port circuit coupled to said peripheral bus and coupled to said peripheral device, wherein said parallel port circuit includes: a data buffer configured to receive write data from said peripheral bus of said computer system; a control unit coupled to said data buffer and configured to cause said write data to be latched within said data buffer in response to a write cycle to said parallel port executed by said processing unit, wherein said control unit is further configured to generate a handshake signal to said peripheral device to indicate that said write data is contained by said data buffer; a time-out counter coupled to said control unit and configured to count a predetermined time period following said assertion of said handshake signal; a status register coupled to said control unit and including an error bit, wherein said control unit is configured to set said error bit if said peripheral device fails to assert an acknowledge signal indicating receipt of said write data before an expiration of said predetermined time period; and a configuration register coupled to said control unit, wherein said configuration register is configured to store a configuration value to control whether a non-maskable interrupt signal or a parallel port interrupt signal is asserted in response to said expiration of said predetermined time period; wherein, in a first mode of operation set by said configuration value stored in said configuration register, if said peripheral device fails to assert said acknowledge signal indicating receipt of said write data within said predetermined time period, said control unit initiates an abort cycle on said peripheral bus and asserts said non-maskable interrupt signal; and wherein, in a second mode of operation set by said configuration value in said configuration register, if said peripheral device fails to assert said acknowledge signal indicating receipt of said write data within said predetermined time period, said control unit releases said processing unit from said write cycle and asserts said parallel port interrupt signal.
Claim 2
Dependent Claim
364 words
A computer system comprising: a processing unit; a local bus coupled to said processing unit; a peripheral bus; a peripheral bus bridge coupled to said local bus and said peripheral bus; a peripheral device; and a parallel port circuit coupled to said peripheral bus and coupled to said peripheral device, wherein said parallel port circuit includes: a data buffer configured to receive write data from said peripheral bus of said computer system; a control unit coupled to said data buffer and configured to cause said write data to be latched within said data buffer in response to a write cycle to said parallel port executed by said processing unit, wherein said control unit is further configured to generate a handshake signal to said peripheral device to indicate that said write data is contained by said data buffer; a time-out counter coupled to said control unit and configured to count a predetermined time period following said assertion of said handshake signal; a status register coupled to said control unit and including an error bit, wherein said control unit is configured to set said error bit if said peripheral device fails to assert an acknowledge signal indicating receipt of said write data before an expiration of said predetermined time period; and a configuration register coupled to said control unit, wherein said configuration register is configured to store a configuration value to control whether a non-maskable interrupt signal or a parallel port interrupt signal is asserted in response to said expiration of said predetermined time period; wherein, in a first mode of operation set by said configuration value stored in said configuration register, if said peripheral device fails to assert said acknowledge signal indicating receipt of said write data within said predetermined time period, said control unit initiates an abort cycle on said peripheral bus and asserts said non-maskable interrupt signal; and wherein, in a second mode of operation set by said configuration value in said configuration register, if said peripheral device fails to assert said acknowledge signal indicating receipt of said write data within said predetermined time period, said control unit releases said processing unit from said write cycle and asserts said parallel port interrupt signal.
Claim 3
Dependent Claim
17 words
The computer system as recited in claim 1 wherein said handshake signal includes a data strobe signal.
Claim 4
Dependent Claim
16 words
The computer system as recited in claim 1 wherein said data buffer includes a latching circuit.
Claim 5
Dependent Claim
19 words
The computer system as recited in claim 1 wherein said predetermined time period of said time-out counter is programmable.
Claim 6
Dependent Claim
283 words
The computer system as recited in claim 1 wherein said data buffer is a bidirectional buffer and is configured to receive read data from said peripheral device wherein said control unit is configured to cause said read data to be latched within said data buffer in response to a read cycle to said parallel port executed by said processing unit, wherein said control unit is further configured to generate a second handshake signal to said peripheral device to indicate that said read data is required to be provided to said data buffer; wherein said time-out counter coupled to said control unit is configured to count a second predetermined time period following said assertion of said second handshake signal; wherein said control unit is configured to set a second error bit in said status register if said peripheral device fails to assert a second acknowledge signal indicating receipt of said read data before an expiration of said second predetermined time period; and wherein said configuration register is configured to store a configuration value to control whether a non-maskable interrupt or a parallel port interrupt is asserted in response to said expiration of said second predetermined time period; wherein, in a first mode of operation set by said configuration value, if said peripheral device fails to assert said second acknowledge signal indicating receipt of said read data within said second predetermined time period, said control unit asserts said non-maskable interrupt signal; wherein, in a second mode of operation set by said configuration value, if said peripheral device fails to assert said second acknowledge signal indicating receipt of said read data within said second predetermined time period, said control unit asserts said parallel port interrupt signal.
Claim 7
Dependent Claim
55 words
The computer system as recited in claim 5 wherein in response to said non-maskable interrupt signal or said parallel port interrupt signal, read data associated with said read cycle received at said data buffer is identified as valid or invalid and said read cycle is re-executed if said read data is indicated to be invalid.
Claim 8
Dependent Claim
29 words
The computer system of claim 1, wherein write data associated with a subsequent write cycle is discarded if said subsequent write cycle is initiated after said predetermined time period.
Claim 9
Dependent Claim
25 words
The computer system as recited in claim 1, wherein said peripheral bus is a PCI bus and said peripheral bus bridge is a PCI bridge.
Claim 10
Dependent Claim
27 words
The computer system as recited in claim 8, wherein said initiation of an abort cycle includes asserting a PCI STOP signal and deasserting a PCI DEVSEL signal.
Claim 11
Independent Claim
194 words
A method for operating a parallel port of a computer system including a processing unit, a local bus, a peripheral bus, a peripheral bus bridge and a peripheral device, said method comprising: executing a write cycle on said peripheral bus of said computer system; latching data within a data buffer of said parallel port in response to said write cycle; providing a data strobe signal to said peripheral device; initiating the countdown of a predetermined time period; waiting for an acknowledge signal from said peripheral device; initiating an abort cycle on said peripheral bus in a first mode of operation if said acknowledge signal is not provided from said peripheral device within said predetermined time period; setting an error bit within a status register if said acknowledge signal is not provided from said peripheral device within said predetermined time period; and asserting an interrupt signal to said processing unit if said acknowledge signal is not provided from said peripheral device within said predetermined time period; wherein said interrupt signal is selectable as a non-maskable interrupt signal in said first mode of operation and a parallel port interrupt signal in a second mode of operation.
Claim 12
Independent Claim
194 words
A method for operating a parallel port of a computer system including a processing unit, a local bus, a peripheral bus, a peripheral bus bridge and a peripheral device, said method comprising: executing a write cycle on said peripheral bus of said computer system; latching data within a data buffer of said parallel port in response to said write cycle; providing a data strobe signal to said peripheral device; initiating the countdown of a predetermined time period; waiting for an acknowledge signal from said peripheral device; initiating an abort cycle on said peripheral bus in a first mode of operation if said acknowledge signal is not provided from said peripheral device within said predetermined time period; setting an error bit within a status register if said acknowledge signal is not provided from said peripheral device within said predetermined time period; and asserting an interrupt signal to said processing unit if said acknowledge signal is not provided from said peripheral device within said predetermined time period; wherein said interrupt signal is selectable as a non-maskable interrupt signal in said first mode of operation and a parallel port interrupt signal in a second mode of operation.
Claim 13
Dependent Claim
33 words
The method for operating a parallel port of a computer system as recited in claim 10, wherein said peripheral bus is a PCI bus and said peripheral bus bridge is a PCI bridge.
Claim 14
Dependent Claim
39 words
The method for operating a parallel port of a computer system as recited in claim 11, wherein said step of initiating an abort signal includes the steps of asserting a PCI STOP signal and deasserting a PCI DEVSEL signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |